Electrical environment within the silicon-on-insulator MOSFET structure

CMOS technology with its maturity and flexibility has provided avenues for constant performance improvement of VLSI circuits and at the same time achieved dimensional shrinkage of the circuits. Time has come now to be creative in finding ways to design and develop circuits for the next generation with further reduction of dimensions. Reports indicate that Silicon-on Insulator (SOI) device respond positively to many problems that stem from dimensional shrinkage and thus shows high potential for the development of low voltage, low power, highspeed circuits with better radiation hardness [1-6]. Literature also indicates that there are many unknowns, especially about the SOI MOSFET parameter influence on the device performance as the device dimension gradually reduces. In this presentation we will present a comparative study of the SOI based transistor structures and their simulated electrical responses under the external influence. In particular we have focused our attention in finding the variations in device characteristics as the channel dimension changes. Efforts are also made to document how the active silicon dimension effects the internal environment. Results clearly depict significant influences of the external parameters, namely gate and drain bias voltages. As expected, shrinkage of the channel dimension nonlinearly affects the device parameters. Both NMOS and PMOS devices are used to understand the effect of channel length shrinkage on the internal electric environment, the band diagram and the drain current. The NMOS transistor used for analysis has a 20 nm thick gate oxide and 0.5 μm deep active uniformly doped silicon layer with a doping concentration of 3 x 10¹⁵ atoms/cm³. The first set of simulation deals with the observation of potential distribution inside SOI MOSFETs of different channel length when applied gate bias voltage is varied keeping the drain voltage at 0V. Fig. 1 (a) and 1 (b) show the observed potential distribution within the SOI devices with channel lengths of 1.3 and 0.4 μms respectively when IV gate voltage is applied. We believe that the formation of the closed loop in the potential profile indicates the existence of a floating body potential. The resultant potential distributions clearly exhibit the confinement as well as the shape change of the floating potential region as a function of channel length shrinkage. The peak e-field magnitude within the closed potential loop for both 1.3 μm and 0.4 μm channel devices are over 10 KV/cm and our observations indicate that as the channel reduces the e-field moves towards the gate. This variation could be attributed to the charge redistribution due to the close proximity of the depletion charges at the drain and source junction. Further reduction of channel length results in a disappearance of the closed potential loop depicting, we think, the nonexistence of the floating body potential. The drain-gate coupling and the subthreshold value are also affected by the reduction o f the channel length as shown in fig. 2. We observe a subthreshold value of 83.02 mV/dec for 1.3 μm device and a value of 95.71 mV/dec for 0.4 μm device. Dimension of the active silicon layer also significantly influence the device behavior. The disappearance of the floating body potential in thin SOI device structure is due to the full depletion of the active silicon region. Additionally, application of a bias voltage at the back gate provides an avenue to manipulate device characteristics by creating depletion or an accumulation region near the buried insulator. All these effects are also studied in SOI PMOS MOSFET. Information gathered is helping us to develop better understanding of the device internal activities and providing avenues to predict device output characteristics more accurately.