Efficient schemes are presented for concurrent detection of errors produced by physical failures during the normal operation of typical VLSI implementations of programmable logic arrays (PLAs) and read-only memories (ROMs). Comprehensive error detection is provided for both permanent and nonpermanent (transient/intermittent) faults. The schemes are based on general fault models and are applicable to various modified implementations of PLAs and ROMs. Fault avoidance for certain classes of failures is ensured by suggested mask-level design rules. A low-overhead solution is provided to the problem of concurrent error detection in a variety of VLSI logic arrays.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Publisher||IEEE Computer Society|
|Number of pages||5|
|State||Published - Dec 1 1985|
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