Abstract
The authors present an efficient algorithm to minimize the layout area by taking the physical sizes of each line, variable net spacing, contact offset, diffusion line offset, and metal line offset into consideration. This algorithm can be used as a postprocessing step for the gate matrix layout. Significant reduction in the layout area, compared to results without performing layout compaction, is achieved.
| Original language | English (US) |
|---|---|
| Title of host publication | Eighth Annu Int Phoenix Conf Comput Commun 1989 Conf Proc |
| Editors | Anon |
| Publisher | IEEE Computer Society |
| Pages | 533-537 |
| Number of pages | 5 |
| State | Published - 1989 |
| Event | Eighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings - Scottsdale, AZ, USA Duration: Mar 22 1989 → Mar 24 1989 |
Other
| Other | Eighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings |
|---|---|
| City | Scottsdale, AZ, USA |
| Period | 3/22/89 → 3/24/89 |
ASJC Scopus subject areas
- General Engineering