Efficient algorithm for gate matrix compactions

Cliff Yungchin Hou, Chien Yi Roger Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The authors present an efficient algorithm to minimize the layout area by taking the physical sizes of each line, variable net spacing, contact offset, diffusion line offset, and metal line offset into consideration. This algorithm can be used as a postprocessing step for the gate matrix layout. Significant reduction in the layout area, compared to results without performing layout compaction, is achieved.

Original languageEnglish (US)
Title of host publicationEighth Annu Int Phoenix Conf Comput Commun 1989 Conf Proc
Editors Anon
PublisherIEEE Computer Society
Pages533-537
Number of pages5
StatePublished - 1989
EventEighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings - Scottsdale, AZ, USA
Duration: Mar 22 1989Mar 24 1989

Other

OtherEighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings
CityScottsdale, AZ, USA
Period3/22/893/24/89

ASJC Scopus subject areas

  • Engineering(all)

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    Hou, C. Y., & Chen, C. Y. R. (1989). Efficient algorithm for gate matrix compactions. In Anon (Ed.), Eighth Annu Int Phoenix Conf Comput Commun 1989 Conf Proc (pp. 533-537). IEEE Computer Society.