TY - GEN
T1 - Effects of transistor reordering on the performance of MOS digital circuits
AU - Carlson, Bradley S.
AU - Roger Chen, C. Y.
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - Many CAD researchers have taken advantage of the freedom to permute series connected transistors in MOS digital circuits in an attempt to decrease layout area without addressing the effect this has on the timing performance of the circuit. Such transistor reordering (or permutations), although will not change the logical behavior of a circuit, can have significant and profound effects on the timing behavior of the circuit. Therefore, the effect of transistor reordering on the timing behavior of MOS circuits is investigated in this paper. The investigation is performed by analyzing the transient response of Series Connected MOS Structures (SCMS's) using SPICE. The investigation shows that the effect of transistor reordering on the timing performance of a MOS logic gate varies significantly depending on transistor strengths, stack height, load capacitance and critical input signal transition time. Circuits for which the effect of transistor reordering on timing is insignificant are clearly identified.
AB - Many CAD researchers have taken advantage of the freedom to permute series connected transistors in MOS digital circuits in an attempt to decrease layout area without addressing the effect this has on the timing performance of the circuit. Such transistor reordering (or permutations), although will not change the logical behavior of a circuit, can have significant and profound effects on the timing behavior of the circuit. Therefore, the effect of transistor reordering on the timing behavior of MOS circuits is investigated in this paper. The investigation is performed by analyzing the transient response of Series Connected MOS Structures (SCMS's) using SPICE. The investigation shows that the effect of transistor reordering on the timing performance of a MOS logic gate varies significantly depending on transistor strengths, stack height, load capacitance and critical input signal transition time. Circuits for which the effect of transistor reordering on timing is insignificant are clearly identified.
UR - http://www.scopus.com/inward/record.url?scp=0041977519&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0041977519&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.1992.271318
DO - 10.1109/MWSCAS.1992.271318
M3 - Conference contribution
AN - SCOPUS:0041977519
T3 - Midwest Symposium on Circuits and Systems
SP - 121
EP - 124
BT - 1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
Y2 - 9 August 1992 through 12 August 1992
ER -