Effects of transistor reordering on the performance of MOS digital circuits

Bradley S. Carlson, C. Y. Roger Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Many CAD researchers have taken advantage of the freedom to permute series connected transistors in MOS digital circuits in an attempt to decrease layout area without addressing the effect this has on the timing performance of the circuit. Such transistor reordering (or permutations), although will not change the logical behavior of a circuit, can have significant and profound effects on the timing behavior of the circuit. Therefore, the effect of transistor reordering on the timing behavior of MOS circuits is investigated in this paper. The investigation is performed by analyzing the transient response of Series Connected MOS Structures (SCMS's) using SPICE. The investigation shows that the effect of transistor reordering on the timing performance of a MOS logic gate varies significantly depending on transistor strengths, stack height, load capacitance and critical input signal transition time. Circuits for which the effect of transistor reordering on timing is insignificant are clearly identified.

Original languageEnglish (US)
Title of host publication1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages121-124
Number of pages4
ISBN (Electronic)0780305108
DOIs
StatePublished - Jan 1 1992
Event35th Midwest Symposium on Circuits and Systems, MWSCAS 1992 - Washington, United States
Duration: Aug 9 1992Aug 12 1992

Publication series

NameMidwest Symposium on Circuits and Systems
Volume1992-August
ISSN (Print)1548-3746

Conference

Conference35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
CountryUnited States
CityWashington
Period8/9/928/12/92

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Carlson, B. S., & Roger Chen, C. Y. (1992). Effects of transistor reordering on the performance of MOS digital circuits. In 1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems (pp. 121-124). [271318] (Midwest Symposium on Circuits and Systems; Vol. 1992-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.1992.271318