Many CAD researchers have taken advantage of the freedom to permute series connected transistors in MOS digital circuits in an attempt to decrease layout area without addressing the effect this has on the timing performance of the circuit. Such transistor reordering (or permutations), although will not change the logical behavior of a circuit, can have significant and profound effects on the timing behavior of the circuit. Therefore, the effect of transistor reordering on the timing behavior of MOS circuits is investigated in this paper. The investigation is performed by analyzing the transient response of Series Connected MOS Structures (SCMS's) using SPICE. The investigation shows that the effect of transistor reordering on the timing performance of a MOS logic gate varies significantly depending on transistor strengths, stack height, load capacitance and critical input signal transition time. Circuits for which the effect of transistor reordering on timing is insignificant are clearly identified.