Dual independent layout generation of arbitrary circuit topologies

Bradley S. Carlson, Chien Yi Roger Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An algorithm is presented which performs automatic layout generation for arbitrary MOS transistor networks with flexible topology for dual independent layouts. The algorithm operates on arbitrary MOS transistor network topologies (including nonplanar), and determines an arrangement of transistors and subcircuits such that the area of the generated layout is minimized The algorithm utilizes a new tree representation which is capable of representing circuits with arbitrary topologies.

Original languageEnglish (US)
Title of host publication1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages528-531
Number of pages4
ISBN (Electronic)0780305108
DOIs
StatePublished - Jan 1 1992
Event35th Midwest Symposium on Circuits and Systems, MWSCAS 1992 - Washington, United States
Duration: Aug 9 1992Aug 12 1992

Publication series

NameMidwest Symposium on Circuits and Systems
Volume1992-August
ISSN (Print)1548-3746

Conference

Conference35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
CountryUnited States
CityWashington
Period8/9/928/12/92

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Carlson, B. S., & Chen, C. Y. R. (1992). Dual independent layout generation of arbitrary circuit topologies. In 1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems (pp. 528-531). [271270] (Midwest Symposium on Circuits and Systems; Vol. 1992-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.1992.271270