TY - GEN
T1 - Dual independent layout generation of arbitrary circuit topologies
AU - Carlson, Bradley S.
AU - Roger Chen, C. Y.
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - An algorithm is presented which performs automatic layout generation for arbitrary MOS transistor networks with flexible topology for dual independent layouts. The algorithm operates on arbitrary MOS transistor network topologies (including nonplanar), and determines an arrangement of transistors and subcircuits such that the area of the generated layout is minimized The algorithm utilizes a new tree representation which is capable of representing circuits with arbitrary topologies.
AB - An algorithm is presented which performs automatic layout generation for arbitrary MOS transistor networks with flexible topology for dual independent layouts. The algorithm operates on arbitrary MOS transistor network topologies (including nonplanar), and determines an arrangement of transistors and subcircuits such that the area of the generated layout is minimized The algorithm utilizes a new tree representation which is capable of representing circuits with arbitrary topologies.
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U2 - 10.1109/MWSCAS.1992.271270
DO - 10.1109/MWSCAS.1992.271270
M3 - Conference contribution
AN - SCOPUS:85065731507
T3 - Midwest Symposium on Circuits and Systems
SP - 528
EP - 531
BT - 1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
Y2 - 9 August 1992 through 12 August 1992
ER -