Dual independent cell generation

Bradley S. Carlson; Chien Yi Roger Chen; Uminder Singh

Dual independent cell generation

Bradley S. Carlson, Chien Yi Roger Chen, Uminder Singh

Department of Electrical Engineering & Computer Science

Research output: Chapter in Book/Entry/Poem › Conference contribution

Abstract

A two-stage linear-time optimization algorithm is presented for dual independent layout styles. The first stage is based on a new tree representation of the complex gate. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding. The optimization algorithm is applicable to many VLSI layout styles. The algorithm is applied to the M³ layout style, and examples of generated layouts are shown. Starting from a switching expression, the algorithm always produces an optimal solution, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence such that the layout contains a minimum number of diffusion gaps (second stage).

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	IEEE Computer Society
Pages	1636-1639
Number of pages	4
Volume	2
State	Published - 1990
Event	1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) - New Orleans, LA, USA Duration: May 1 1990 → May 3 1990

Other

Other	1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4)
City	New Orleans, LA, USA
Period	5/1/90 → 5/3/90

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

@inproceedings{49a2b167cf234c54b6fef25ae229b984,

title = "Dual independent cell generation",

abstract = "A two-stage linear-time optimization algorithm is presented for dual independent layout styles. The first stage is based on a new tree representation of the complex gate. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding. The optimization algorithm is applicable to many VLSI layout styles. The algorithm is applied to the M3 layout style, and examples of generated layouts are shown. Starting from a switching expression, the algorithm always produces an optimal solution, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence such that the layout contains a minimum number of diffusion gaps (second stage).",

author = "Carlson, {Bradley S.} and Chen, {Chien Yi Roger} and Uminder Singh",

year = "1990",

language = "English (US)",

volume = "2",

pages = "1636--1639",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "IEEE Computer Society",

address = "United States",

note = "1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) ; Conference date: 01-05-1990 Through 03-05-1990",

}

TY - GEN

T1 - Dual independent cell generation

AU - Carlson, Bradley S.

AU - Chen, Chien Yi Roger

AU - Singh, Uminder

PY - 1990

Y1 - 1990

N2 - A two-stage linear-time optimization algorithm is presented for dual independent layout styles. The first stage is based on a new tree representation of the complex gate. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding. The optimization algorithm is applicable to many VLSI layout styles. The algorithm is applied to the M3 layout style, and examples of generated layouts are shown. Starting from a switching expression, the algorithm always produces an optimal solution, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence such that the layout contains a minimum number of diffusion gaps (second stage).

AB - A two-stage linear-time optimization algorithm is presented for dual independent layout styles. The first stage is based on a new tree representation of the complex gate. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding. The optimization algorithm is applicable to many VLSI layout styles. The algorithm is applied to the M3 layout style, and examples of generated layouts are shown. Starting from a switching expression, the algorithm always produces an optimal solution, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence such that the layout contains a minimum number of diffusion gaps (second stage).

UR - http://www.scopus.com/inward/record.url?scp=0025638182&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025638182&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0025638182

VL - 2

SP - 1636

EP - 1639

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE Computer Society

T2 - 1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4)

Y2 - 1 May 1990 through 3 May 1990

ER -

Dual independent cell generation

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ASJC Scopus subject areas

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