Dual independent cell generation

Bradley S. Carlson, Chien Yi Roger Chen, Uminder Singh

Research output: Chapter in Book/Entry/PoemConference contribution


A two-stage linear-time optimization algorithm is presented for dual independent layout styles. The first stage is based on a new tree representation of the complex gate. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding. The optimization algorithm is applicable to many VLSI layout styles. The algorithm is applied to the M3 layout style, and examples of generated layouts are shown. Starting from a switching expression, the algorithm always produces an optimal solution, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence such that the layout contains a minimum number of diffusion gaps (second stage).

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE Computer Society
Number of pages4
StatePublished - 1990
Event1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) - New Orleans, LA, USA
Duration: May 1 1990May 3 1990


Other1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4)
CityNew Orleans, LA, USA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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