Detailed placement with net length constraints

B. Halpin, N. Sehgal, C. Y.R. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Increasing demands created by Systems-On-Chip (SOC) and process advances have increased the difficulty of timing driven placement. The primary issue in SOC is timing closure. This requires us to look at timing at all design levels, especially placement. Recently, several promising approaches for timing-driven placement have been presented using net length constraints for timing optimization (Alpert et al., 2001). A Net Length Constraint (NLC) is an upper limit on a net's length. These net-constrained global placement techniques give excellent timing results by meeting NLCs on timing-critical nets. These works focused only on global NLC placement. Detailed placement and legalization are important steps in the placement flow. Current algorithms, which are not NLC aware, give back the gains from global NLC placement. The contributions of this paper are a new NLC global placement rebalancing method and two detailed placement algorithms that work in conjunction with the recursive bisection net-constrained global placer (Alpert et al., 2001). The first detailed placer uses grid-based placement and transportation solving to assign instances to the grid. The second detailed placer uses simulated annealing to optimize placement for NLC. On benchmark circuits from MCNC and Intel Corporation, the grid and simulated annealing placers are able to achieve placements which exceed constraints by, on average only, 2.7% and 1.9%, respectively.

Original languageEnglish (US)
Title of host publicationProceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
EditorsYehya Ismail, Wael Badawy
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages22-27
Number of pages6
ISBN (Electronic)076951944X, 9780769519449
DOIs
StatePublished - Jan 1 2003
Event3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 - Calgary, Canada
Duration: Jun 30 2003Jul 2 2003

Publication series

NameProceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Other

Other3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
CountryCanada
CityCalgary
Period6/30/037/2/03

Keywords

  • Automatic control
  • Circuit simulation
  • Constraint optimization
  • Delay
  • Design engineering
  • Optimization methods
  • Simulated annealing
  • Timing
  • Transportation
  • Very large scale integration

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Halpin, B., Sehgal, N., & Chen, C. Y. R. (2003). Detailed placement with net length constraints. In Y. Ismail, & W. Badawy (Eds.), Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 (pp. 22-27). [1212999] (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IWSOC.2003.1212999