TY - JOUR
T1 - Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes
AU - Xie, Qing
AU - Wang, Yanzhi
AU - Pedram, Massoud
N1 - Funding Information:
This research is sponsored in part by grants from the Defense Advanced Research Projects Agency and the National Science Foundation .
PY - 2014/6
Y1 - 2014/6
N2 - Soft-edge flip-flop (SEFF) based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by enabling the opportunistic time borrowing. The application of this technique to the near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections. In particular, delay lines in SEFFs have to be over-designed to provide larger transparency windows to overcome the variation in path delays, which causes them to consume more power. To address this issue, this paper presents a novel way of designing delay lines in SEFFs to have a large enough transparency window size and low power consumption. Two types of linear pipeline design problems using the SEFFs are formulated and solved: (1) designing energy-delay optimal pipelines for the general usage that requires SEFFs to operate in both the near-threshold and super-threshold regimes, and (2) designing minimum energy consumed pipelines for particular use case with a minimum operating frequency constraint. Design methods are presented to derive requisite pipeline design parameters (i.e.; depth and sizing of delay lines in SEFFs) and operating conditions (i.e.; supply voltage and operating frequency of the design) in presence of process-induced variations. HSPICE simulation results using ISCAS benchmarks demonstrate the efficacy of the presented design methods.
AB - Soft-edge flip-flop (SEFF) based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by enabling the opportunistic time borrowing. The application of this technique to the near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections. In particular, delay lines in SEFFs have to be over-designed to provide larger transparency windows to overcome the variation in path delays, which causes them to consume more power. To address this issue, this paper presents a novel way of designing delay lines in SEFFs to have a large enough transparency window size and low power consumption. Two types of linear pipeline design problems using the SEFFs are formulated and solved: (1) designing energy-delay optimal pipelines for the general usage that requires SEFFs to operate in both the near-threshold and super-threshold regimes, and (2) designing minimum energy consumed pipelines for particular use case with a minimum operating frequency constraint. Design methods are presented to derive requisite pipeline design parameters (i.e.; depth and sizing of delay lines in SEFFs) and operating conditions (i.e.; supply voltage and operating frequency of the design) in presence of process-induced variations. HSPICE simulation results using ISCAS benchmarks demonstrate the efficacy of the presented design methods.
KW - Near-threshold computing
KW - Pipelined circuits design
KW - Process variation
KW - Soft-edge flip-flop
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U2 - 10.1016/j.vlsi.2013.11.003
DO - 10.1016/j.vlsi.2013.11.003
M3 - Article
AN - SCOPUS:84901618195
SN - 0167-9260
VL - 47
SP - 318
EP - 328
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
IS - 3
ER -