Design optimization of sense amplifiers using deeply-scaled FinFET devices

Alireza Shafaei; Yanzhi Wang; Antonio Petraglia; Massoud Pedram

doi:10.1109/ISQED.2015.7085439

Design optimization of sense amplifiers using deeply-scaled FinFET devices

Alireza Shafaei, Yanzhi Wang, Antonio Petraglia, Massoud Pedram

Research output: Chapter in Book/Entry/Poem › Conference contribution

2 Scopus citations

Abstract

This paper presents the design optimization of sense amplifiers made of deeply-scaled (7nm) FinFET devices in order to improve the energy efficiency of cache memories, while robust operation of the sense amplifier under process variations is achieved. To this end, an analytical solution for deriving the minimum voltage difference that can be correctly sensed between the sense amplifier inputs, considering process variations, is presented. Device parameters and transistor sizing of the sense amplifier are then optimized in order to further increase the cache energy efficiency. The optimized sense amplifier design has 2-fold lower input voltage difference compared with the baseline counterpart, which according to the architecture-level simulations, causes 26% reduction in the total energy consumption of an L1 cache memory.

Original language	English (US)
Title of host publication	Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
Publisher	IEEE Computer Society
Pages	280-283
Number of pages	4
ISBN (Electronic)	9781479975815
DOIs	https://doi.org/10.1109/ISQED.2015.7085439
State	Published - Apr 13 2015
Externally published	Yes
Event	16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States Duration: Mar 2 2015 → Mar 4 2015

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2015-April
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Other

Other	16th International Symposium on Quality Electronic Design, ISQED 2015
Country/Territory	United States
City	Santa Clara
Period	3/2/15 → 3/4/15

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

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10.1109/ISQED.2015.7085439

Cite this

Shafaei, A., Wang, Y., Petraglia, A., & Pedram, M. (2015). Design optimization of sense amplifiers using deeply-scaled FinFET devices. In Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015 (pp. 280-283). Article 7085439 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2015-April). IEEE Computer Society. https://doi.org/10.1109/ISQED.2015.7085439

Design optimization of sense amplifiers using deeply-scaled FinFET devices. / Shafaei, Alireza; Wang, Yanzhi; Petraglia, Antonio et al.
Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society, 2015. p. 280-283 7085439 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2015-April).

Research output: Chapter in Book/Entry/Poem › Conference contribution

Shafaei, A, Wang, Y, Petraglia, A & Pedram, M 2015, Design optimization of sense amplifiers using deeply-scaled FinFET devices. in Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015., 7085439, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2015-April, IEEE Computer Society, pp. 280-283, 16th International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, United States, 3/2/15. https://doi.org/10.1109/ISQED.2015.7085439

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abstract = "This paper presents the design optimization of sense amplifiers made of deeply-scaled (7nm) FinFET devices in order to improve the energy efficiency of cache memories, while robust operation of the sense amplifier under process variations is achieved. To this end, an analytical solution for deriving the minimum voltage difference that can be correctly sensed between the sense amplifier inputs, considering process variations, is presented. Device parameters and transistor sizing of the sense amplifier are then optimized in order to further increase the cache energy efficiency. The optimized sense amplifier design has 2-fold lower input voltage difference compared with the baseline counterpart, which according to the architecture-level simulations, causes 26% reduction in the total energy consumption of an L1 cache memory.",

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Design optimization of sense amplifiers using deeply-scaled FinFET devices

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