Design, implementation and evaluation of parallel pipelined STAP on parallel computers

A. Choudhary, Wei Keng Liao, D. Weiner, P. Varshney, R. Linderman, M. Linderman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particular the paper describes the issues involved in parallelization, our approach to parallelization and performance results on an Intel Paragon. The paper also discusses the process of developing software for such an application on parallel computers when latency and throughput are both considered together and presents tradeoffs considered with respect to inter and intra-task communication and data redistribution. The results show that not only scalable performance was achieved for individual component tasks of STAP but linear speedups were obtained for the integrated task performance, both for latency as well as throughput. Results are presented for up to 236 compute nodes (limited by the machine size available to us). Another interesting observation made from the implementation results is that performance improvement due to the assignment of additional processors to one task can improve the performance of other tasks without any increase in the number of processors assigned to them. Normally, this cannot be predicted by theoretical analysis.

Original languageEnglish (US)
Title of host publicationProceedings of the 1st Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing, IPPS/SPDP 1998
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages220-225
Number of pages6
ISBN (Electronic)0818684038, 9780818684036
DOIs
StatePublished - Jan 1 1998
Event1st Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing, IPPS/SPDP 1998 - Orlando, United States
Duration: Mar 30 1998Apr 3 1998

Publication series

NameProceedings of the 1st Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing, IPPS/SPDP 1998
Volume1998-March

Other

Other1st Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing, IPPS/SPDP 1998
CountryUnited States
CityOrlando
Period3/30/984/3/98

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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    Choudhary, A., Liao, W. K., Weiner, D., Varshney, P., Linderman, R., & Linderman, M. (1998). Design, implementation and evaluation of parallel pipelined STAP on parallel computers. In Proceedings of the 1st Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing, IPPS/SPDP 1998 (pp. 220-225). (Proceedings of the 1st Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing, IPPS/SPDP 1998; Vol. 1998-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPPS.1998.669914