Abstract
Leakage power consumption has recently become a great concern for modern embedded systems. FinFET technologies, power gating, and near-and super-threshold regimes can significantly reduce the power consumption. However, there lacks a comprehensive analysis of jointly applying the aforementioned power saving techniques. In this paper, we investigate the application of power gating to FinFET circuits operating in near-and super-threshold voltage regimes for embedded system applications. A joint optimization algorithm is proposed to determine the width/length, position and threshold type of the sleep transistor together with the operating voltage constrained to a certain deadline, and with the goal of minimizing energy per operation. Experimental results demonstrate that the proposed algorithm achieves up to 99:9% energy reductions when compared to the near-threshold approach without power gating and 95:3% when compared to deadline-free optimization.
Original language | English (US) |
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Title of host publication | GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017 |
Publisher | Association for Computing Machinery |
Pages | 427-430 |
Number of pages | 4 |
Volume | Part F127756 |
ISBN (Electronic) | 9781450349727 |
DOIs | |
State | Published - May 10 2017 |
Event | 27th Great Lakes Symposium on VLSI, GLSVLSI 2017 - Banff, Canada Duration: May 10 2017 → May 12 2017 |
Other
Other | 27th Great Lakes Symposium on VLSI, GLSVLSI 2017 |
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Country/Territory | Canada |
City | Banff |
Period | 5/10/17 → 5/12/17 |
ASJC Scopus subject areas
- Engineering(all)