Deadline-aware joint optimization of sleep transistor and supply voltage for FinFET based embedded systems

Huimei Cheng, Ji Li, Jeffrey Draper, Shahin Nazarian, Yanzhi Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


Leakage power consumption has recently become a great concern for modern embedded systems. FinFET technologies, power gating, and near-and super-threshold regimes can significantly reduce the power consumption. However, there lacks a comprehensive analysis of jointly applying the aforementioned power saving techniques. In this paper, we investigate the application of power gating to FinFET circuits operating in near-and super-threshold voltage regimes for embedded system applications. A joint optimization algorithm is proposed to determine the width/length, position and threshold type of the sleep transistor together with the operating voltage constrained to a certain deadline, and with the goal of minimizing energy per operation. Experimental results demonstrate that the proposed algorithm achieves up to 99:9% energy reductions when compared to the near-threshold approach without power gating and 95:3% when compared to deadline-free optimization.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PublisherAssociation for Computing Machinery
Number of pages4
VolumePart F127756
ISBN (Electronic)9781450349727
StatePublished - May 10 2017
Event27th Great Lakes Symposium on VLSI, GLSVLSI 2017 - Banff, Canada
Duration: May 10 2017May 12 2017


Other27th Great Lakes Symposium on VLSI, GLSVLSI 2017

ASJC Scopus subject areas

  • Engineering(all)


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