Deadline-aware joint optimization of sleep transistor and supply voltage for FinFET based embedded systems

Leakage power consumption has recently become a great concern for modern embedded systems. FinFET technologies, power gating, and near-and super-threshold regimes can significantly reduce the power consumption. However, there lacks a comprehensive analysis of jointly applying the aforementioned power saving techniques. In this paper, we investigate the application of power gating to FinFET circuits operating in near-and super-threshold voltage regimes for embedded system applications. A joint optimization algorithm is proposed to determine the width/length, position and threshold type of the sleep transistor together with the operating voltage constrained to a certain deadline, and with the goal of minimizing energy per operation. Experimental results demonstrate that the proposed algorithm achieves up to 99:9% energy reductions when compared to the near-threshold approach without power gating and 95:3% when compared to deadline-free optimization.