TY - GEN
T1 - Deadline-aware joint optimization of sleep transistor and supply voltage for FinFET based embedded systems
AU - Cheng, Huimei
AU - Li, Ji
AU - Draper, Jeffrey
AU - Nazarian, Shahin
AU - Wang, Yanzhi
N1 - Publisher Copyright:
© 2017 ACM.
PY - 2017/5/10
Y1 - 2017/5/10
N2 - Leakage power consumption has recently become a great concern for modern embedded systems. FinFET technologies, power gating, and near-and super-threshold regimes can significantly reduce the power consumption. However, there lacks a comprehensive analysis of jointly applying the aforementioned power saving techniques. In this paper, we investigate the application of power gating to FinFET circuits operating in near-and super-threshold voltage regimes for embedded system applications. A joint optimization algorithm is proposed to determine the width/length, position and threshold type of the sleep transistor together with the operating voltage constrained to a certain deadline, and with the goal of minimizing energy per operation. Experimental results demonstrate that the proposed algorithm achieves up to 99:9% energy reductions when compared to the near-threshold approach without power gating and 95:3% when compared to deadline-free optimization.
AB - Leakage power consumption has recently become a great concern for modern embedded systems. FinFET technologies, power gating, and near-and super-threshold regimes can significantly reduce the power consumption. However, there lacks a comprehensive analysis of jointly applying the aforementioned power saving techniques. In this paper, we investigate the application of power gating to FinFET circuits operating in near-and super-threshold voltage regimes for embedded system applications. A joint optimization algorithm is proposed to determine the width/length, position and threshold type of the sleep transistor together with the operating voltage constrained to a certain deadline, and with the goal of minimizing energy per operation. Experimental results demonstrate that the proposed algorithm achieves up to 99:9% energy reductions when compared to the near-threshold approach without power gating and 95:3% when compared to deadline-free optimization.
UR - http://www.scopus.com/inward/record.url?scp=85021236789&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85021236789&partnerID=8YFLogxK
U2 - 10.1145/3060403.3060424
DO - 10.1145/3060403.3060424
M3 - Conference contribution
AN - SCOPUS:85021236789
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 427
EP - 430
BT - GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PB - Association for Computing Machinery
T2 - 27th Great Lakes Symposium on VLSI, GLSVLSI 2017
Y2 - 10 May 2017 through 12 May 2017
ER -