Datapath cell design strategy for channelless routing

Naresh K. Sehgal, Chien Yi Roger Chen, John M. Acken

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In many advanced microprocessors, including all recent Intel microprocessors, the datapath is implemented in a bit-sliced structure, in which data inputs and control signals are arranged orthogonally. As of today, physical layout of such datapaths is performed manually, and has been shown to be a major productivity bottleneck in many recent designs. In this paper, a methodology is presented for layout generation of such bit-sliced structures using library cells. Special techniques are proposed for layout planning and connectivity of library cells to meet the high density requirements of datapath design. Experiments on real examples have shown very promising results. Significant improvements have been achieved over conventional approaches.

Original languageEnglish (US)
Title of host publicationProceedings of the Annual IEEE International ASIC Conference and Exhibit
PublisherIEEE Computer Society
Pages122-125
Number of pages4
StatePublished - 1994
Externally publishedYes
EventProceedings of the 7th IEEE International ASIC Conference and Exhibit - Rochester, NY, USA
Duration: Sep 19 1994Sep 23 1994

Other

OtherProceedings of the 7th IEEE International ASIC Conference and Exhibit
CityRochester, NY, USA
Period9/19/949/23/94

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Sehgal, N. K., Chen, C. Y. R., & Acken, J. M. (1994). Datapath cell design strategy for channelless routing. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit (pp. 122-125). IEEE Computer Society.