Concurrent Error Detection in Highly Structured Logic Arrays

W. Kent Fuchs, Chien Yi Roger Chen, Jacob A. Abraham

Research output: Contribution to journalArticlepeer-review

25 Scopus citations


Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLA’s) are introduced in this paper. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLA’s) and read-only memories (ROM’s). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirectional errors. The technique achieves the totally self-checking (TSC) goal of producing a detectable noncode word as the first erroneous output of the array due to a fault by ensuring that the encoded arrays are strongly fault secure (SFS). The arrays are also strongly code disjoint (SCD) and thereby eliminate the need for separate input code-word checkers. The second approach relies on a detailed examination of decoder layouts resulting in fault avoidance through layout rules, which avoid failures causing unidirectional errors. Efficient parity techniques are shown to provide a low overhead solution to concurrent error detection when coupled with appropriate fault avoidance techniques. Key Words — Concurrent error detection, fault avoidance, highly structured logic arrays, PLA, ROM, strongly code disjoint, strongly fault secure.

Original languageEnglish (US)
Pages (from-to)583-594
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Issue number4
StatePublished - Aug 1987
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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