TY - GEN
T1 - Comparison of silicon-on-insulator and Body-on-Insulator FinFET based digital circuits with consideration on self-heating effects
AU - Feng, Peijie
AU - Ghosh, Prasanta
PY - 2011
Y1 - 2011
N2 - In recent years FinFET emerges as a promising device to assure the desired performance in the sub-22 nm regime. Among various FinFETs, SOI FinFET shows suppressed leakage current and superior short channel effects. However, it suffers from increased self-heating effect (SHE) due to the adaptation of a low thermal conductivity buried silicon dioxide layer and a ultra thin fin body. Bulk FinFET, on the other hand, mitigates the heating issue at the cost of the leakage current. Body-on-Insulator (BOI) FinFET alleviates, to some extent, the aforementioned downsides of both SOI and bulk FinFET but with the increased fabrication complexity [1]. Here, we report extensive simulation of BOI and SOI FinFETs using technology computer aided design (TCAD) [2] and for the first time, present evaluation of BOI and SOI FinFET based digital circuits and demonstrate that in actuality SHE is comparable for both circuits under low voltage bias.
AB - In recent years FinFET emerges as a promising device to assure the desired performance in the sub-22 nm regime. Among various FinFETs, SOI FinFET shows suppressed leakage current and superior short channel effects. However, it suffers from increased self-heating effect (SHE) due to the adaptation of a low thermal conductivity buried silicon dioxide layer and a ultra thin fin body. Bulk FinFET, on the other hand, mitigates the heating issue at the cost of the leakage current. Body-on-Insulator (BOI) FinFET alleviates, to some extent, the aforementioned downsides of both SOI and bulk FinFET but with the increased fabrication complexity [1]. Here, we report extensive simulation of BOI and SOI FinFETs using technology computer aided design (TCAD) [2] and for the first time, present evaluation of BOI and SOI FinFET based digital circuits and demonstrate that in actuality SHE is comparable for both circuits under low voltage bias.
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U2 - 10.1109/ISDRS.2011.6135230
DO - 10.1109/ISDRS.2011.6135230
M3 - Conference contribution
AN - SCOPUS:84857206907
SN - 9781457717550
T3 - 2011 International Semiconductor Device Research Symposium, ISDRS 2011
BT - 2011 International Semiconductor Device Research Symposium, ISDRS 2011
T2 - 2011 International Semiconductor Device Research Symposium, ISDRS 2011
Y2 - 7 December 2011 through 9 December 2011
ER -