TY - JOUR
T1 - Capacitive neural network with neuro-transistors
AU - Wang, Zhongrui
AU - Rao, Mingyi
AU - Han, Jin Woo
AU - Zhang, Jiaming
AU - Lin, Peng
AU - Li, Yunning
AU - Li, Can
AU - Song, Wenhao
AU - Asapu, Shiva
AU - Midya, Rivu
AU - Zhuo, Ye
AU - Jiang, Hao
AU - Yoon, Jung Ho
AU - Upadhyay, Navnidhi Kumar
AU - Joshi, Saumil
AU - Hu, Miao
AU - Strachan, John Paul
AU - Barnell, Mark
AU - Wu, Qing
AU - Wu, Huaqiang
AU - Qiu, Qinru
AU - Williams, R. Stanley
AU - Xia, Qiangfei
AU - Yang, J. Joshua
N1 - Funding Information:
This work was supported in part by the U.S. Air Force Research Laboratory (AFRL) (Grant No. FA8750-15-2-0044), the Defense Advanced Research Projects Agency (DARPA) (Contract No. D17PC00304), and the National Science Foundation (NSF) (ECCS-1253073). Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of AFRL. H.W. was supported by the Beijing Advanced Innovation Center for Future Chip (ICFC) and NSFC (61674089, 61674092). Part of the device fabrication was conducted in the clean room of the Center for Hierarchical Manufacturing (CHM), an NSF Nanoscale Science and Engineering Center (NSEC) located at the University of Massachusetts Amherst.
Publisher Copyright:
© 2018, The Author(s).
PY - 2018/12/1
Y1 - 2018/12/1
N2 - Experimental demonstration of resistive neural networks has been the recent focus of hardware implementation of neuromorphic computing. Capacitive neural networks, which call for novel building blocks, provide an alternative physical embodiment of neural networks featuring a lower static power and a better emulation of neural functionalities. Here, we develop neuro-transistors by integrating dynamic pseudo-memcapacitors as the gates of transistors to produce electronic analogs of the soma and axon of a neuron, with “leaky integrate-and-fire” dynamics augmented by a signal gain on the output. Paired with non-volatile pseudo-memcapacitive synapses, a Hebbian-like learning mechanism is implemented in a capacitive switching network, leading to the observed associative learning. A prototypical fully integrated capacitive neural network is built and used to classify inputs of signals.
AB - Experimental demonstration of resistive neural networks has been the recent focus of hardware implementation of neuromorphic computing. Capacitive neural networks, which call for novel building blocks, provide an alternative physical embodiment of neural networks featuring a lower static power and a better emulation of neural functionalities. Here, we develop neuro-transistors by integrating dynamic pseudo-memcapacitors as the gates of transistors to produce electronic analogs of the soma and axon of a neuron, with “leaky integrate-and-fire” dynamics augmented by a signal gain on the output. Paired with non-volatile pseudo-memcapacitive synapses, a Hebbian-like learning mechanism is implemented in a capacitive switching network, leading to the observed associative learning. A prototypical fully integrated capacitive neural network is built and used to classify inputs of signals.
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U2 - 10.1038/s41467-018-05677-5
DO - 10.1038/s41467-018-05677-5
M3 - Article
C2 - 30097585
AN - SCOPUS:85051526103
SN - 2041-1723
VL - 9
JO - Nature Communications
JF - Nature Communications
IS - 1
M1 - 3208
ER -