Assured VLSI design with formal verification

Jang Dae Kim, Shiu Kai Chin

Research output: Chapter in Book/Entry/PoemConference contribution

1 Scopus citations


Design and verification using formal logic extends existing VLSI design methods and tools. Such an extension provides rigorous support for design and verification at various levels of abstraction. Our design methodology combines design verification by mechanized theorem proving with conventional CAD tools. The theorem proving environment allows us to relate low level boolean implementations and high level arithmetic and instruction set specifications. We use the Higher-Order Logic theorem prover (HOL) to verify correctness relations between implementations and specifications. We use existing CAD tools to synthesize physical layouts and validate low level electrical and timing properties. Our CAD systems are Mentor Graphics GDT and MAGIC. To verify our design methodology, we fabricated a serial pipelined multiplier that is formally verified. Bit-serial circuits are widely used in signal processing. The multiplier chip was fabricated through MOSIS and worked correctly.

Original languageEnglish (US)
Title of host publicationCOMPASS - Proceedings of the Annual Conference on Computer Assurance
Editors Anon
PublisherIEEE Computer Society
Number of pages10
StatePublished - 1997
EventProceedings of the 1997 12th Annual Conference on Computer Assurance, COMPASS'97 - Gaithersburg, MD, USA
Duration: Jun 16 1997Jun 19 1997


OtherProceedings of the 1997 12th Annual Conference on Computer Assurance, COMPASS'97
CityGaithersburg, MD, USA

ASJC Scopus subject areas

  • Hardware and Architecture


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