Area-efficient scaling-free DFT/FFT design using stochastic computing

Bo Yuan; Yanzhi Wang; Zhongfeng Wang

doi:10.1109/ISCAS.2016.7539207

Area-efficient scaling-free DFT/FFT design using stochastic computing

Bo Yuan, Yanzhi Wang, Zhongfeng Wang

Department of Electrical Engineering & Computer Science

Research output: Chapter in Book/Entry/Poem › Conference contribution

1 Scopus citations

Abstract

Among various discrete transforms, discrete Fourier transformation (DFT) is the most important technique that performs Fourier analysis in various practical applications, such as digital signal processing, wireless communications, to name a few. Due to its ultra-high computing complexity as O(N2), in practice the N-point DFT is usually performed in the form of fast Fourier transformation (FFT) with complexity as O(NlogN). Despite this significant reduction in computing complexity, the hardware cost of the multiplication-intensive N-point FFT is still very prohibitive; especially for many large-scale applications that requires large N.

Original language	English (US)
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2904
Number of pages	1
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7539207
State	Published - Jul 29 2016
Event	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: May 22 2016 → May 25 2016

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2016-July
ISSN (Print)	0271-4310

Other

Other	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Country/Territory	Canada
City	Montreal
Period	5/22/16 → 5/25/16

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2016.7539207

Cite this

Yuan, B., Wang, Y., & Wang, Z. (2016). Area-efficient scaling-free DFT/FFT design using stochastic computing. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (pp. 2904). Article 7539207 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2016.7539207

Area-efficient scaling-free DFT/FFT design using stochastic computing. / Yuan, Bo; Wang, Yanzhi; Wang, Zhongfeng.
ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2016. p. 2904 7539207 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July).

Research output: Chapter in Book/Entry/Poem › Conference contribution

Yuan, B, Wang, Y & Wang, Z 2016, Area-efficient scaling-free DFT/FFT design using stochastic computing. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7539207, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2016-July, Institute of Electrical and Electronics Engineers Inc., pp. 2904, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 5/22/16. https://doi.org/10.1109/ISCAS.2016.7539207

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AB - Among various discrete transforms, discrete Fourier transformation (DFT) is the most important technique that performs Fourier analysis in various practical applications, such as digital signal processing, wireless communications, to name a few. Due to its ultra-high computing complexity as O(N2), in practice the N-point DFT is usually performed in the form of fast Fourier transformation (FFT) with complexity as O(NlogN). Despite this significant reduction in computing complexity, the hardware cost of the multiplication-intensive N-point FFT is still very prohibitive; especially for many large-scale applications that requires large N.

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Area-efficient scaling-free DFT/FFT design using stochastic computing

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