Area-efficient error-resilient discrete fourier transformation design using stochastic computing

Bo Yuan, Yanzhi Wang, Zhongfeng Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Discrete Fourier Transformation (DFT)/Fast Fourier Transformation (FFT) are the widely used techniques in numerous modern signal processing applications. In general, because of their inherent multiplication-intensive characteristics, the hardware implementations of DFT/FFT usually require a large amount of hardware resource, which limits their applications in area-constraint scenarios. To overcome this challenge, this paper, for the first time, proposes area-efficient error-resilient DFT designs using stochastic computing. By leveraging low-complexity stochastic multipliers, two types of stochastic DFT design are presented with significant reduction in overall area. Analysis results show that compared with the conventional design, the proposed two 256-point stochastic DFT designs achieve 76% and 62% reduction in area, respectively. More importantly, these stochastic DFT designs also show much stronger error-resilience, which is very attractive in nanoscale CMOS era.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2016 - Proceedings of the 2016 ACM Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages33-38
Number of pages6
Volume18-20-May-2016
ISBN (Electronic)9781450342742
DOIs
StatePublished - May 18 2016
Event26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016 - Boston, United States
Duration: May 18 2016May 20 2016

Other

Other26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016
CountryUnited States
CityBoston
Period5/18/165/20/16

Keywords

  • DFT
  • Error resilience
  • FFT
  • Stochastic computing
  • VLSI

ASJC Scopus subject areas

  • Engineering(all)

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