TY - GEN
T1 - Area-efficient error-resilient discrete fourier transformation design using stochastic computing
AU - Yuan, Bo
AU - Wang, Yanzhi
AU - Wang, Zhongfeng
N1 - Publisher Copyright:
© 2016 ACM.
PY - 2016/5/18
Y1 - 2016/5/18
N2 - Discrete Fourier Transformation (DFT)/Fast Fourier Transformation (FFT) are the widely used techniques in numerous modern signal processing applications. In general, because of their inherent multiplication-intensive characteristics, the hardware implementations of DFT/FFT usually require a large amount of hardware resource, which limits their applications in area-constraint scenarios. To overcome this challenge, this paper, for the first time, proposes area-efficient error-resilient DFT designs using stochastic computing. By leveraging low-complexity stochastic multipliers, two types of stochastic DFT design are presented with significant reduction in overall area. Analysis results show that compared with the conventional design, the proposed two 256-point stochastic DFT designs achieve 76% and 62% reduction in area, respectively. More importantly, these stochastic DFT designs also show much stronger error-resilience, which is very attractive in nanoscale CMOS era.
AB - Discrete Fourier Transformation (DFT)/Fast Fourier Transformation (FFT) are the widely used techniques in numerous modern signal processing applications. In general, because of their inherent multiplication-intensive characteristics, the hardware implementations of DFT/FFT usually require a large amount of hardware resource, which limits their applications in area-constraint scenarios. To overcome this challenge, this paper, for the first time, proposes area-efficient error-resilient DFT designs using stochastic computing. By leveraging low-complexity stochastic multipliers, two types of stochastic DFT design are presented with significant reduction in overall area. Analysis results show that compared with the conventional design, the proposed two 256-point stochastic DFT designs achieve 76% and 62% reduction in area, respectively. More importantly, these stochastic DFT designs also show much stronger error-resilience, which is very attractive in nanoscale CMOS era.
KW - DFT
KW - Error resilience
KW - FFT
KW - Stochastic computing
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=84974712282&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84974712282&partnerID=8YFLogxK
U2 - 10.1145/2902961.2902978
DO - 10.1145/2902961.2902978
M3 - Conference contribution
AN - SCOPUS:84974712282
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 33
EP - 38
BT - GLSVLSI 2016 - Proceedings of the 2016 ACM Great Lakes Symposium on VLSI
PB - Association for Computing Machinery
T2 - 26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016
Y2 - 18 May 2016 through 20 May 2016
ER -