TY - GEN
T1 - Architectural design and complexity analysis of large-scale cortical simulation on a hybrid computing platform
AU - Wu, Qing
AU - Qiu, Qinru
AU - Linderman, Richard
AU - Burns, Daniel
AU - Moore, Michael
AU - Fitzgerald, Dennis
PY - 2007
Y1 - 2007
N2 - Research and development in modeling and simulation of human cognizance functions requires a high-performance computing platform for manipulating large-scale mathematical models. Traditional computing architectures cannot fulfill the attendant needs in terms of arithmetic computation and communication bandwidth. In this work, we propose a novel hybrid computing architecture for the simulation and evaluation of large-scale associative neural memory models. The proposed architecture achieves very high computing and communication performances by combining the technologies of hardware-accelerated computing, parallel distributed data operation and the publish/subscribe protocol. Analysis has been done on the computation and data bandwidth demands for implementing a large-scale Brain-State-in-a-Box (BSB) model. Compared to the traditional computing architecture, the proposed architecture can achieve at least 100X speedup.
AB - Research and development in modeling and simulation of human cognizance functions requires a high-performance computing platform for manipulating large-scale mathematical models. Traditional computing architectures cannot fulfill the attendant needs in terms of arithmetic computation and communication bandwidth. In this work, we propose a novel hybrid computing architecture for the simulation and evaluation of large-scale associative neural memory models. The proposed architecture achieves very high computing and communication performances by combining the technologies of hardware-accelerated computing, parallel distributed data operation and the publish/subscribe protocol. Analysis has been done on the computation and data bandwidth demands for implementing a large-scale Brain-State-in-a-Box (BSB) model. Compared to the traditional computing architecture, the proposed architecture can achieve at least 100X speedup.
UR - http://www.scopus.com/inward/record.url?scp=34548728202&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34548728202&partnerID=8YFLogxK
U2 - 10.1109/CISDA.2007.368154
DO - 10.1109/CISDA.2007.368154
M3 - Conference contribution
AN - SCOPUS:34548728202
SN - 1424407001
SN - 9781424407002
T3 - Proceedings of the 2007 IEEE Symposium on Computational Intelligence in Security and Defense Applications, CISDA 2007
SP - 201
EP - 205
BT - Proceedings of the 2007 IEEE Symposium on Computational Intelligence in Security and Defense Applications, CISDA 2007
T2 - 2007 IEEE Symposium on Computational Intelligence in Security and Defense Applications, CISDA 2007
Y2 - 1 April 2007 through 5 April 2007
ER -