@inproceedings{9852727265c04a5e95d88c39b2d52fb8,
title = "Analysis of deeply scaled multi-gate devices with design centering across multiple voltage regimes",
abstract = "This work aims at finding a design-centered FinFET model with small geometric for circuit and system level simulations and performance prediction of next-generation systems on chip. A number of devices including the ITRS 7nm multi-gate device are used as examples. While adjusting design parameters for the transistors, a design centering step is included in which the gate workfunction is carefully adjusted to account for the increased power dissipation due to gate length variations. Using a cross-layer framework, compact device models and standard cell libraries are built up for circuit-level and system-level simulations. Simulation results of SRAM cells as well as some combinational/sequential benchmark circuits are shown to compare the device performance in different technologies.",
keywords = "Design centering, FinFET, Near-threshold computing, SRAM",
author = "Shuang Chen and Xue Lin and Alireza Shafaei and Yanzhi Wang and Massoud Pedram",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 ; Conference date: 05-10-2015 Through 08-10-2015",
year = "2015",
month = nov,
day = "20",
doi = "10.1109/S3S.2015.7333517",
language = "English (US)",
series = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",
}