An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes

Xue Lin, Yanzhi Wang, Shahin Nazarian, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Digital near-threshold logic circuits have recently been proposed for applications in the ultra-low power end of the design spectrum, where the performance is of secondary importance. However, the characteristics of MOS transistors operating in the near-threshold region are very different from those in the strong-inversion region. This paper first derives the logical effort and parasitic delay values for logic gates in multiple voltage (sub/near/super- threshold) regimes based on the transregional model. The transregional model shows higher accuracy for both sub- and near-threshold regions compared with the subthreshold model. Furthermore, the derived near-threshold logical effort method is subsequently used for delay optimization of circuits operating in both near- and super-threshold regimes. In order to achieve this goal, a joint optimization of transistor sizing and adaptive body biasing is proposed and optimally solved using geometric programming. Experimental results show that our improved logical effort-based optimization framework provides a performance improvement of up to 40.1% over the conventional logical effort method.

Original languageEnglish (US)
Title of host publicationProceedings of the 15th International Symposium on Quality Electronic Design, ISQED 2014
PublisherIEEE Computer Society
Pages249-256
Number of pages8
ISBN (Print)9781479939466
DOIs
StatePublished - Jan 1 2014
Event15th International Symposium on Quality Electronic Design, ISQED 2014 - Santa Clara, CA, United States
Duration: Mar 3 2014Mar 5 2014

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other15th International Symposium on Quality Electronic Design, ISQED 2014
CountryUnited States
CitySanta Clara, CA
Period3/3/143/5/14

Keywords

  • Delay optimization
  • Logical effort
  • Sub/near-threshold

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Lin, X., Wang, Y., Nazarian, S., & Pedram, M. (2014). An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes. In Proceedings of the 15th International Symposium on Quality Electronic Design, ISQED 2014 (pp. 249-256). [6783333] (Proceedings - International Symposium on Quality Electronic Design, ISQED). IEEE Computer Society. https://doi.org/10.1109/ISQED.2014.6783333