An exploration of applying gate-length-biasing techniques to deeply-scaled FinFETs operating in multiple voltage regimes

Tiansong Cui, Ji Li, Yanzhi Wang, Shahin Nazarian, Massoud Pedram

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

With the aggressive downscaling of process technologies and the importance of battery-powered systems, reducing leakage power consumption has become a crucial design challenge for IC designers. In addition, the traditional bulk CMOS technologies face significant challenges related to short-channel effects and process variations. FinFET devices have attracted a lot of attention as an alternative to bulk CMOS in sub-32nm technology nodes. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in near- A nd super-threshold ($V-T$ ) operation regimes. The impacts of cell-level and transistor-level Gate-Length Biasing (GLB) on circuit speed and leakage power are studied using a 7 nm FinFET technology.

Original languageEnglish (US)
Pages (from-to)172-183
Number of pages12
JournalIEEE Transactions on Emerging Topics in Computing
Volume6
Issue number2
DOIs
StatePublished - Apr 1 2018

Keywords

  • 7 nm FinFET technology
  • Gate-length biasing (GLB)
  • leakage power
  • near-threshold computing

ASJC Scopus subject areas

  • Computer Science (miscellaneous)
  • Information Systems
  • Human-Computer Interaction
  • Computer Science Applications

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