An exploration of applying gate-length-biasing techniques to deeply-scaled FinFETs operating in multiple voltage regimes

With the aggressive downscaling of process technologies and the importance of battery-powered systems, reducing leakage power consumption has become a crucial design challenge for IC designers. In addition, the traditional bulk CMOS technologies face significant challenges related to short-channel effects and process variations. FinFET devices have attracted a lot of attention as an alternative to bulk CMOS in sub-32nm technology nodes. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in near- A nd super-threshold ($V-T$ ) operation regimes. The impacts of cell-level and transistor-level Gate-Length Biasing (GLB) on circuit speed and leakage power are studied using a 7 nm FinFET technology.