An efficient gate delay model for VLSI design

Ting Wei Chiang; C. Y.Roger Chen; Wei Yu Chen

doi:10.1109/ICCD.2007.4601938

An efficient gate delay model for VLSI design

Ting Wei Chiang, C. Y.Roger Chen, Wei Yu Chen

Department of Electrical Engineering & Computer Science

Research output: Chapter in Book/Entry/Poem › Conference contribution

2 Scopus citations

Abstract

Accurate estimation of gate delays is essential for timing-related CAD tools. CAD researchers tend to use Elmore delay model for estimating gate delays. Since Elmore delay model was primarily developed for estimating interconnection delay, when applied to gate delay estimation, there will be significant inaccuracy. In this paper, by embedding concepts of electronic theories into switch-level analysis, a simple and efficient delay model for gates of general types (such as NAND, NOR, and complex gates) is proposed. Experimental data show that the proposed gate delay model consistently achieves high accuracy (typically within around 2% of SPICE simulations).

Original language	English (US)
Title of host publication	2007 IEEE International Conference on Computer Design, ICCD 2007
Pages	450-455
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2007.4601938
State	Published - 2007
Event	2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States Duration: Oct 7 2007 → Oct 10 2007

Publication series

Name	2007 IEEE International Conference on Computer Design, ICCD 2007

Other

Other	2007 IEEE International Conference on Computer Design, ICCD 2007
Country/Territory	United States
City	Lake Tahoe, CA
Period	10/7/07 → 10/10/07

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2007.4601938

Cite this

Chiang, TW, Chen, CYR & Chen, WY 2007, An efficient gate delay model for VLSI design. in 2007 IEEE International Conference on Computer Design, ICCD 2007., 4601938, 2007 IEEE International Conference on Computer Design, ICCD 2007, pp. 450-455, 2007 IEEE International Conference on Computer Design, ICCD 2007, Lake Tahoe, CA, United States, 10/7/07. https://doi.org/10.1109/ICCD.2007.4601938

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abstract = "Accurate estimation of gate delays is essential for timing-related CAD tools. CAD researchers tend to use Elmore delay model for estimating gate delays. Since Elmore delay model was primarily developed for estimating interconnection delay, when applied to gate delay estimation, there will be significant inaccuracy. In this paper, by embedding concepts of electronic theories into switch-level analysis, a simple and efficient delay model for gates of general types (such as NAND, NOR, and complex gates) is proposed. Experimental data show that the proposed gate delay model consistently achieves high accuracy (typically within around 2% of SPICE simulations).",

author = "Chiang, {Ting Wei} and Chen, {C. Y.Roger} and Chen, {Wei Yu}",

year = "2007",

doi = "10.1109/ICCD.2007.4601938",

language = "English (US)",

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series = "2007 IEEE International Conference on Computer Design, ICCD 2007",

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AB - Accurate estimation of gate delays is essential for timing-related CAD tools. CAD researchers tend to use Elmore delay model for estimating gate delays. Since Elmore delay model was primarily developed for estimating interconnection delay, when applied to gate delay estimation, there will be significant inaccuracy. In this paper, by embedding concepts of electronic theories into switch-level analysis, a simple and efficient delay model for gates of general types (such as NAND, NOR, and complex gates) is proposed. Experimental data show that the proposed gate delay model consistently achieves high accuracy (typically within around 2% of SPICE simulations).

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M3 - Conference contribution

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T3 - 2007 IEEE International Conference on Computer Design, ICCD 2007

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ER -

An efficient gate delay model for VLSI design

Abstract

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