An efficient gate delay model for VLSI design

Ting Wei Chiang, C. Y.Roger Chen, Wei Yu Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Accurate estimation of gate delays is essential for timing-related CAD tools. CAD researchers tend to use Elmore delay model for estimating gate delays. Since Elmore delay model was primarily developed for estimating interconnection delay, when applied to gate delay estimation, there will be significant inaccuracy. In this paper, by embedding concepts of electronic theories into switch-level analysis, a simple and efficient delay model for gates of general types (such as NAND, NOR, and complex gates) is proposed. Experimental data show that the proposed gate delay model consistently achieves high accuracy (typically within around 2% of SPICE simulations).

Original languageEnglish (US)
Title of host publication2007 IEEE International Conference on Computer Design, ICCD 2007
Pages450-455
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States
Duration: Oct 7 2007Oct 10 2007

Publication series

Name2007 IEEE International Conference on Computer Design, ICCD 2007

Other

Other2007 IEEE International Conference on Computer Design, ICCD 2007
CountryUnited States
CityLake Tahoe, CA
Period10/7/0710/10/07

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Chiang, T. W., Chen, C. Y. R., & Chen, W. Y. (2007). An efficient gate delay model for VLSI design. In 2007 IEEE International Conference on Computer Design, ICCD 2007 (pp. 450-455). [4601938] (2007 IEEE International Conference on Computer Design, ICCD 2007). https://doi.org/10.1109/ICCD.2007.4601938