Algorithms to simplify multi-clock/edge timing constraints

Veerapaneni Nagbhushan, C. Y.Roger Chen

Research output: Chapter in Book/Entry/PoemConference contribution

1 Scopus citations

Abstract

The use of multiple clocks has become a common practice in modern microprocessor design. With multiple clocks, the timing specifications have become complicated and tend to go beyond the ability of single-clock based CAD tools. This paper first introduces the concept of timing specification transformation. Then, this paper describes algorithms for transforming an interface timing specification with multiple clocks/edges into an equivalent specification with a single clock/edge for combinational circuit blocks. It formulates a new optimization problem, which is important but has never been addressed by CAD researchers. It identifies conditions under which this transformation can be performed efficiently without any loss of timing budget. The algorithm can be used to simplify the constraints to drive many synthesis and optimization algorithms.

Original languageEnglish (US)
Title of host publication2007 IEEE International Conference on Computer Design, ICCD 2007
Pages444-449
Number of pages6
DOIs
StatePublished - 2007
Event2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States
Duration: Oct 7 2007Oct 10 2007

Publication series

Name2007 IEEE International Conference on Computer Design, ICCD 2007

Other

Other2007 IEEE International Conference on Computer Design, ICCD 2007
Country/TerritoryUnited States
CityLake Tahoe, CA
Period10/7/0710/10/07

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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