ACE: An Analog Cell Emulator for Dependability Study of NAND Flash Memory

Reliability is one of the primary concerns in modern SSD designs. Despite the benefits of high performance, low power consumption, and increased density, the vendors struggle with the reliability of user data due to various sources of analog noise. There were consorted efforts and studies to improve the reliability issues in SSDs, but we still need experimenting tools that present analog states of errors. To address this issue, we propose a novel NAND flash memory emulator, called ACE (Analog Cell Emulator), that uses threshold voltages for dependability studies. The proposed emulator maintains data as analog values through threshold voltage modeling, enabling emulation of endurance, retention, and disturbance errors of flash memory. To reduce the emulation overhead, metadata in a cell, page, and block are managed separately, and emulation is performed while reading rather than periodic error emulation. We evaluate the accuracy of ACE by comparing its signal with that of actual devices, with the results indicating that the signal differences are up to 4.3%. Additionally, we analyze two reliability enhancement techniques, ECC (Error Correction Code) and read-retry, using ACE with adjusted reference voltages. This analysis, which could not be feasible with existing emulators, demonstrates the advantages of the proposed analog emulator.