Abstract
Dynamic voltage and frequency scaling (DVFS) has been studied for well over a decade. Nevertheless, existing DVFS transition overhead models suffer from significant inaccuracies; for example, by incorrectly accounting for the effect of DC-DC converters, frequency synthesizers, voltage, and frequency change policies on energy losses incurred during mode transitions. Incorrect and/or inaccurate DVFS transition overhead models prevent one from determining the precise break-even time and thus forfeit some of the energy saving that is ideally achievable. This paper introduces accurate DVFS transition overhead models for both energy consumption and delay. In particular, we redefine the DVFS transition overhead including the underclocking-related losses in a DVFS-enabled microprocessor, additional inductor IR losses, and power losses due to discontinuous-mode DC-DC conversion. We report the transition overheads for a desktop, a mobile and a low-power representative processor. We also present DVFS transition overhead macromodel for use by high-level DVFS schedulers.
| Original language | English (US) |
|---|---|
| Article number | 6504549 |
| Pages (from-to) | 695-708 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 32 |
| Issue number | 5 |
| DOIs | |
| State | Published - 2013 |
| Externally published | Yes |
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Keywords
- Delay and energy overhead
- dynamic voltage and frequency scaling (DVFS)
- macromodel
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Graphics and Computer-Aided Design
- Software
Cite this
Accurate modeling of the delay and energy overhead of dynamic voltage and frequency scaling in modern microprocessors. / Park, Sangyoung; Park, Jaehyun; Shin, Donghwa; Wang, Yanzhi; Xie, Qing; Pedram, Massoud; Chang, Naehyuck.
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 5, 6504549, 2013, p. 695-708.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Accurate modeling of the delay and energy overhead of dynamic voltage and frequency scaling in modern microprocessors
AU - Park, Sangyoung
AU - Park, Jaehyun
AU - Shin, Donghwa
AU - Wang, Yanzhi
AU - Xie, Qing
AU - Pedram, Massoud
AU - Chang, Naehyuck
PY - 2013
Y1 - 2013
N2 - Dynamic voltage and frequency scaling (DVFS) has been studied for well over a decade. Nevertheless, existing DVFS transition overhead models suffer from significant inaccuracies; for example, by incorrectly accounting for the effect of DC-DC converters, frequency synthesizers, voltage, and frequency change policies on energy losses incurred during mode transitions. Incorrect and/or inaccurate DVFS transition overhead models prevent one from determining the precise break-even time and thus forfeit some of the energy saving that is ideally achievable. This paper introduces accurate DVFS transition overhead models for both energy consumption and delay. In particular, we redefine the DVFS transition overhead including the underclocking-related losses in a DVFS-enabled microprocessor, additional inductor IR losses, and power losses due to discontinuous-mode DC-DC conversion. We report the transition overheads for a desktop, a mobile and a low-power representative processor. We also present DVFS transition overhead macromodel for use by high-level DVFS schedulers.
AB - Dynamic voltage and frequency scaling (DVFS) has been studied for well over a decade. Nevertheless, existing DVFS transition overhead models suffer from significant inaccuracies; for example, by incorrectly accounting for the effect of DC-DC converters, frequency synthesizers, voltage, and frequency change policies on energy losses incurred during mode transitions. Incorrect and/or inaccurate DVFS transition overhead models prevent one from determining the precise break-even time and thus forfeit some of the energy saving that is ideally achievable. This paper introduces accurate DVFS transition overhead models for both energy consumption and delay. In particular, we redefine the DVFS transition overhead including the underclocking-related losses in a DVFS-enabled microprocessor, additional inductor IR losses, and power losses due to discontinuous-mode DC-DC conversion. We report the transition overheads for a desktop, a mobile and a low-power representative processor. We also present DVFS transition overhead macromodel for use by high-level DVFS schedulers.
KW - Delay and energy overhead
KW - dynamic voltage and frequency scaling (DVFS)
KW - macromodel
UR - http://www.scopus.com/inward/record.url?scp=84876776667&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84876776667&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2012.2235126
DO - 10.1109/TCAD.2012.2235126
M3 - Article
AN - SCOPUS:84876776667
VL - 32
SP - 695
EP - 708
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 5
M1 - 6504549
ER -