A transistor reordering technique for gate matrix layout

Uminder Singh, C. Y.Roger Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the gate matrix layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous works using net-lists and the concept of delayed binding performed only a small subset of the reordering possible with the proposed algorithm. The algorithm has a time complexity of O(E log E) for a design with E equations. The experimental results show a considerable reduction in layout area.

Original languageEnglish (US)
Title of host publication27th ACM/IEEE Design Automation Conference. Proceedings 1990
PublisherIEEE Computer Society
Pages462-467
Number of pages6
ISBN (Print)081869650X
DOIs
StatePublished - Jan 1 1990
Event27th ACM/IEEE Design Automation Conference - Orlando, FL, USA
Duration: Jun 24 1990Jun 28 1990

Publication series

Name27th ACM/IEEE Design Automation Conference. Proceedings 1990

Other

Other27th ACM/IEEE Design Automation Conference
CityOrlando, FL, USA
Period6/24/906/28/90

ASJC Scopus subject areas

  • Engineering(all)

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    Singh, U., & Chen, C. Y. R. (1990). A transistor reordering technique for gate matrix layout. In 27th ACM/IEEE Design Automation Conference. Proceedings 1990 (pp. 462-467). (27th ACM/IEEE Design Automation Conference. Proceedings 1990). IEEE Computer Society. https://doi.org/10.1145/123186.123340