@inproceedings{74939d4773114caeb91370f214b6eb52,
title = "A transistor reordering technique for gate matrix layout",
abstract = "An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the gate matrix layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous works using net-lists and the concept of delayed binding performed only a small subset of the reordering possible with the proposed algorithm. The algorithm has a time complexity of O(E log E) for a design with E equations. The experimental results show a considerable reduction in layout area.",
author = "Uminder Singh and Chen, {C. Y.Roger}",
year = "1990",
doi = "10.1145/123186.123340",
language = "English (US)",
isbn = "081869650X",
series = "27th ACM/IEEE Design Automation Conference. Proceedings 1990",
publisher = "IEEE Computer Society",
pages = "462--467",
booktitle = "27th ACM/IEEE Design Automation Conference. Proceedings 1990",
address = "United States",
note = "27th ACM/IEEE Design Automation Conference ; Conference date: 24-06-1990 Through 28-06-1990",
}