A technique for selecting CMOS transistor orders

Ting Wei Chiang; C. Y.Roger Chen; Wei Yu Chen

doi:10.1109/ICCD.2007.4601936

A technique for selecting CMOS transistor orders

Ting Wei Chiang, C. Y.Roger Chen, Wei Yu Chen

Department of Electrical Engineering & Computer Science

Research output: Chapter in Book/Entry/Poem › Conference contribution

2 Scopus citations

Abstract

Transistor reordering has been known to be effective in reducing delays of a circuit with nearly zero penalties. However, techniques to determine good transistor orders have not been proposed in literature. Previous work on this has to resort to running SPICE for all meaningful transistor orders and selecting a best one, which is extremely time-consuming. This paper proposes an efficient and accurate technique for determining best transistor orders without running SPICE simulations. Experimental results from SPICE3 show that the predictions are very accurate.

Original language	English (US)
Title of host publication	2007 IEEE International Conference on Computer Design, ICCD 2007
Pages	438-443
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2007.4601936
State	Published - 2007
Event	2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States Duration: Oct 7 2007 → Oct 10 2007

Publication series

Name	2007 IEEE International Conference on Computer Design, ICCD 2007

Other

Other	2007 IEEE International Conference on Computer Design, ICCD 2007
Country/Territory	United States
City	Lake Tahoe, CA
Period	10/7/07 → 10/10/07

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2007.4601936

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Chiang, TW, Chen, CYR & Chen, WY 2007, A technique for selecting CMOS transistor orders. in 2007 IEEE International Conference on Computer Design, ICCD 2007., 4601936, 2007 IEEE International Conference on Computer Design, ICCD 2007, pp. 438-443, 2007 IEEE International Conference on Computer Design, ICCD 2007, Lake Tahoe, CA, United States, 10/7/07. https://doi.org/10.1109/ICCD.2007.4601936

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abstract = "Transistor reordering has been known to be effective in reducing delays of a circuit with nearly zero penalties. However, techniques to determine good transistor orders have not been proposed in literature. Previous work on this has to resort to running SPICE for all meaningful transistor orders and selecting a best one, which is extremely time-consuming. This paper proposes an efficient and accurate technique for determining best transistor orders without running SPICE simulations. Experimental results from SPICE3 show that the predictions are very accurate.",

author = "Chiang, {Ting Wei} and Chen, {C. Y.Roger} and Chen, {Wei Yu}",

year = "2007",

doi = "10.1109/ICCD.2007.4601936",

language = "English (US)",

isbn = "1424412587",

series = "2007 IEEE International Conference on Computer Design, ICCD 2007",

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AB - Transistor reordering has been known to be effective in reducing delays of a circuit with nearly zero penalties. However, techniques to determine good transistor orders have not been proposed in literature. Previous work on this has to resort to running SPICE for all meaningful transistor orders and selecting a best one, which is extremely time-consuming. This paper proposes an efficient and accurate technique for determining best transistor orders without running SPICE simulations. Experimental results from SPICE3 show that the predictions are very accurate.

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SN - 9781424412587

T3 - 2007 IEEE International Conference on Computer Design, ICCD 2007

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BT - 2007 IEEE International Conference on Computer Design, ICCD 2007

T2 - 2007 IEEE International Conference on Computer Design, ICCD 2007

Y2 - 7 October 2007 through 10 October 2007

ER -

A technique for selecting CMOS transistor orders

Abstract

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