A technique for selecting CMOS transistor orders

Ting Wei Chiang, C. Y.Roger Chen, Wei Yu Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Transistor reordering has been known to be effective in reducing delays of a circuit with nearly zero penalties. However, techniques to determine good transistor orders have not been proposed in literature. Previous work on this has to resort to running SPICE for all meaningful transistor orders and selecting a best one, which is extremely time-consuming. This paper proposes an efficient and accurate technique for determining best transistor orders without running SPICE simulations. Experimental results from SPICE3 show that the predictions are very accurate.

Original languageEnglish (US)
Title of host publication2007 IEEE International Conference on Computer Design, ICCD 2007
Pages438-443
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States
Duration: Oct 7 2007Oct 10 2007

Publication series

Name2007 IEEE International Conference on Computer Design, ICCD 2007

Other

Other2007 IEEE International Conference on Computer Design, ICCD 2007
CountryUnited States
CityLake Tahoe, CA
Period10/7/0710/10/07

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Chiang, T. W., Chen, C. Y. R., & Chen, W. Y. (2007). A technique for selecting CMOS transistor orders. In 2007 IEEE International Conference on Computer Design, ICCD 2007 (pp. 438-443). [4601936] (2007 IEEE International Conference on Computer Design, ICCD 2007). https://doi.org/10.1109/ICCD.2007.4601936