A survey on neuromorphic computing: Models and hardware

Amar Shrestha, Haowen Fang, Zaidao Mei, Daniel Patrick Rider, Qing Wu, Qinru Qiu

Research output: Contribution to journalArticlepeer-review

Abstract

The explosion of “big data” applications imposes severe challenges of speed and scalability on traditional computer systems. As the performance of traditional Von Neumann machines is greatly hindered by the increasing performance gap between CPU and memory (“known as the memory wall”), neuromorphic computing systems have gained considerable attention. The biology-plausible computing paradigm carries out computing by emulating the charging/discharging process of neuron and synapse potential. The unique spike domain information encoding enables asynchronous event driven computation and communication, and hence has the potential for very high energy efficiency. This survey reviews computing models and hardware platforms of existing neuromorphic computing systems. Neuron and synapse models are first introduced, followed by the discussion on how they will affect hardware design. Case studies of several representative hardware platforms, including their architecture and software ecosystems, are further presented. Lastly we present several future research directions.

Original languageEnglish (US)
Pages (from-to)6-35
Number of pages30
JournalIEEE Circuits and Systems Magazine
Volume22
Issue number2
DOIs
StatePublished - 2022
Externally publishedYes

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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