A probabilistic technique for full-chip leakage estimation

Shaobo Liu, Qinru Qiu, Qing Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

In this paper, we propose a probability-based algorithm to estimate full-chip leakage without knowing layout information, under intra-die and inter-die process variations. Through modeling process variations into a random vector, we show that the standard cell leakage can be modeled as an inverse Gaussian random variable and further demonstrate that full-chip leakage can also be approximated to be an inverse Gaussian random variable. Hence, the leakage estimation problem is reduced to the estimation of the mean value and variance of the full-chip leakage. Experimental results show that the proposed algorithm is over 1000X faster than Monte Carlo simulation while the maximum estimation error is less than 6%.

Original languageEnglish (US)
Title of host publicationISLPED'08
Subtitle of host publicationProceedings of the 2008 International Symposium on Low Power Electronics and Design
Pages205-208
Number of pages4
DOIs
StatePublished - Dec 18 2008
Externally publishedYes
EventISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design - Bangalore, India
Duration: Aug 11 2008Aug 13 2008

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
CountryIndia
CityBangalore
Period8/11/088/13/08

Keywords

  • Leakage estimation
  • VLSI

ASJC Scopus subject areas

  • Engineering(all)

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