In standard cell design, many cell terminals and gates are permutable, and it is important for a channel router to take advantage of this to obtain better results. An efficient hierarchical algorithm is presented to determine the proper positions of permutable gates and cell terminals such that the results of the subsequent channel routing can be significantly improved. Experimental results show that our proposed algorithm considerably reduces the number of tracks and vias, and its time complexity is linear in the number of cell terminals.
|Original language||English (US)|
|Number of pages||8|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Jul 1995|
ASJC Scopus subject areas
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering