A Preprocessor for Improving Channel Routing Hierarchical Pin Permutation

C. Y.Roger Chen; Bradley S. Carlson; Cliff Yungchin Hou

doi:10.1109/43.391738

A Preprocessor for Improving Channel Routing Hierarchical Pin Permutation

C. Y.Roger Chen, Bradley S. Carlson, Cliff Yungchin Hou

Department of Electrical Engineering & Computer Science

Research output: Contribution to journal › Article › peer-review

Abstract

In standard cell design, many cell terminals and gates are permutable, and it is important for a channel router to take advantage of this to obtain better results. An efficient hierarchical algorithm is presented to determine the proper positions of permutable gates and cell terminals such that the results of the subsequent channel routing can be significantly improved. Experimental results show that our proposed algorithm considerably reduces the number of tracks and vias, and its time complexity is linear in the number of cell terminals.

Original language	English (US)
Pages (from-to)	896-903
Number of pages	8
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	14
Issue number	7
DOIs	https://doi.org/10.1109/43.391738
State	Published - Jul 1995

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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abstract = "In standard cell design, many cell terminals and gates are permutable, and it is important for a channel router to take advantage of this to obtain better results. An efficient hierarchical algorithm is presented to determine the proper positions of permutable gates and cell terminals such that the results of the subsequent channel routing can be significantly improved. Experimental results show that our proposed algorithm considerably reduces the number of tracks and vias, and its time complexity is linear in the number of cell terminals.",

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N2 - In standard cell design, many cell terminals and gates are permutable, and it is important for a channel router to take advantage of this to obtain better results. An efficient hierarchical algorithm is presented to determine the proper positions of permutable gates and cell terminals such that the results of the subsequent channel routing can be significantly improved. Experimental results show that our proposed algorithm considerably reduces the number of tracks and vias, and its time complexity is linear in the number of cell terminals.

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A Preprocessor for Improving Channel Routing Hierarchical Pin Permutation

Abstract

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