A novel leakage power reduction technique for CMOS circuit design

Jae Woong Chun, C. Y.Roger Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Scopus citations


Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit types for low-power design centered around inserting controlling transistors between pull-up and pull down circuits as well as between pull-up circuits/pull down circuits and power/ground. We investigate the characteristics of proposed gate types in terms of ability to reduce power consumption and their associated delay overhead. In addition, several variations of drain gating are discussed. In the end, an overall procedure for low-power circuit design is proposed by intelligently mixing various proposed circuit types for gates in the circuits based upon gate criticality analysis. Extensive SPICE simulation results were reported using 45nm, 32nm and 22nm process technologies. Significant power reduction is achieved with zero or little increase in the critical path delay of the overall circuits.

Original languageEnglish (US)
Title of host publication2010 International SoC Design Conference, ISOCC 2010
Number of pages4
StatePublished - Dec 1 2010
Event2010 International SoC Design Conference, ISOCC 2010 - Incheon, Korea, Republic of
Duration: Nov 22 2010Nov 23 2010

Publication series

Name2010 International SoC Design Conference, ISOCC 2010


Other2010 International SoC Design Conference, ISOCC 2010
Country/TerritoryKorea, Republic of


  • Leakage power consumption
  • Low-power design
  • Sleep transistors
  • Transistor stacking

ASJC Scopus subject areas

  • Hardware and Architecture


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