A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks

S. H. Hsiao; C. Y.R. Chen

doi:10.1109/IPPS.1993.262783

A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks

S. H. Hsiao, C. Y.R. Chen

Department of Electrical Engineering & Computer Science

Research output: Chapter in Book/Entry/Poem › Conference contribution

2 Scopus citations

Abstract

Patel (1981) proposed a probabilistic approach to analyze the performance of multiprocessor systems using synchronous multistage interconnection networks (MINs) based on a uniform reference model and the assumption of independent requests. Through extensive simulation, the authors have found that, in many cases, their model will result in rather significant inaccuracy. the factors which cause inaccuracy in Patel's model are investigated in detail. A new queueing model is then proposed and is shown to be very accurate. Since only six states are needed, this new model is very efficient computationally.

Original language	English (US)
Title of host publication	Proceedings of 7th International Parallel Processing Symposium, IPPS 1993
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	773-777
Number of pages	5
ISBN (Electronic)	0818634421, 9780818634420
DOIs	https://doi.org/10.1109/IPPS.1993.262783
State	Published - 1993
Event	7th International Parallel Processing Symposium, IPPS 1993 - Newport, United States Duration: Apr 13 1993 → Apr 16 1993

Publication series

Name	Proceedings of 7th International Parallel Processing Symposium, IPPS 1993

Conference

Conference	7th International Parallel Processing Symposium, IPPS 1993
Country/Territory	United States
City	Newport
Period	4/13/93 → 4/16/93

ASJC Scopus subject areas

Computer Science Applications
Hardware and Architecture
Software
Computational Theory and Mathematics
Computer Networks and Communications

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10.1109/IPPS.1993.262783

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Hsiao, S. H., & Chen, C. Y. R. (1993). A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks. In Proceedings of 7th International Parallel Processing Symposium, IPPS 1993 (pp. 773-777). Article 262783 (Proceedings of 7th International Parallel Processing Symposium, IPPS 1993). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPPS.1993.262783

A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks. / Hsiao, S. H.; Chen, C. Y.R.
Proceedings of 7th International Parallel Processing Symposium, IPPS 1993. Institute of Electrical and Electronics Engineers Inc., 1993. p. 773-777 262783 (Proceedings of 7th International Parallel Processing Symposium, IPPS 1993).

Research output: Chapter in Book/Entry/Poem › Conference contribution

Hsiao, SH & Chen, CYR 1993, A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks. in Proceedings of 7th International Parallel Processing Symposium, IPPS 1993., 262783, Proceedings of 7th International Parallel Processing Symposium, IPPS 1993, Institute of Electrical and Electronics Engineers Inc., pp. 773-777, 7th International Parallel Processing Symposium, IPPS 1993, Newport, United States, 4/13/93. https://doi.org/10.1109/IPPS.1993.262783

Hsiao SH, Chen CYR. A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks. In Proceedings of 7th International Parallel Processing Symposium, IPPS 1993. Institute of Electrical and Electronics Engineers Inc. 1993. p. 773-777. 262783. (Proceedings of 7th International Parallel Processing Symposium, IPPS 1993). doi: 10.1109/IPPS.1993.262783

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A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks

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