Smart cameras with embedded processors will find great use in sensor network applications since they have local processing capabilities. It is very important to consider complexity, area requirements, power consumption and cost when designing image sensor chips for embedded smart cameras. To obtain a higher-resolution image of a region of interest, and address the above issues, we propose to tile multiple lower-resolution, lower-cost embedded smart cameras instead of fabricating a higher-resolution sensor as a single chip. In addition to complexity, area, power and cost advantages, the presented scheme has the benefit of having hierarchical levels of processing, and distributed computation across the tiles. We present our low-resolution smart cameras, which have custom-designed image sensor chips. Then, we provide a detailed comparison of fabricating a higher-resolution sensor as a single chip and tiling lower-resolution embedded smart cameras in terms of bandwidth, clock frequency, area, power, cost and global computations.