Abstract
Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67%, and reduces 53% of communication latency.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019 |
| Publisher | IEEE Computer Society |
| Pages | 20-25 |
| Number of pages | 6 |
| ISBN (Electronic) | 9781728103921 |
| DOIs | |
| State | Published - Apr 23 2019 |
| Event | 20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States Duration: Mar 6 2019 → Mar 7 2019 |
Publication series
| Name | Proceedings - International Symposium on Quality Electronic Design, ISQED |
|---|---|
| Volume | 2019-March |
| ISSN (Print) | 1948-3287 |
| ISSN (Electronic) | 1948-3295 |
Conference
| Conference | 20th International Symposium on Quality Electronic Design, ISQED 2019 |
|---|---|
| Country | United States |
| City | Santa Clara |
| Period | 3/6/19 → 3/7/19 |
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Keywords
- Neuromorphic hardware
- spiking neural network
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
Cite this
A General Framework to Map Neural Networks onto Neuromorphic Processor. / Fang, Haowen; Shrestha, Amar; Zhao, Ziyi; Wang, Yanzhi; Qiu, Qinru.
Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. p. 20-25 8697495 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2019-March).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A General Framework to Map Neural Networks onto Neuromorphic Processor
AU - Fang, Haowen
AU - Shrestha, Amar
AU - Zhao, Ziyi
AU - Wang, Yanzhi
AU - Qiu, Qinru
PY - 2019/4/23
Y1 - 2019/4/23
N2 - Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67%, and reduces 53% of communication latency.
AB - Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67%, and reduces 53% of communication latency.
KW - Neuromorphic hardware
KW - spiking neural network
UR - http://www.scopus.com/inward/record.url?scp=85065191445&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85065191445&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2019.8697495
DO - 10.1109/ISQED.2019.8697495
M3 - Conference contribution
AN - SCOPUS:85065191445
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 20
EP - 25
BT - Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
PB - IEEE Computer Society
ER -