A General Framework to Map Neural Networks onto Neuromorphic Processor

Haowen Fang, Amar Shrestha, Ziyi Zhao, Yanzhi Wang, Qinru Qiu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67%, and reduces 53% of communication latency.

Original languageEnglish (US)
Title of host publicationProceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
PublisherIEEE Computer Society
Pages20-25
Number of pages6
ISBN (Electronic)9781728103921
DOIs
StatePublished - Apr 23 2019
Event20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States
Duration: Mar 6 2019Mar 7 2019

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2019-March
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference20th International Symposium on Quality Electronic Design, ISQED 2019
CountryUnited States
CitySanta Clara
Period3/6/193/7/19

Fingerprint

Neural networks
Hardware
Communication
Distributed computer systems
Parallel processing systems
Fans
Brain
Data storage equipment
Fabrication
Costs

Keywords

  • Neuromorphic hardware
  • spiking neural network

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Fang, H., Shrestha, A., Zhao, Z., Wang, Y., & Qiu, Q. (2019). A General Framework to Map Neural Networks onto Neuromorphic Processor. In Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019 (pp. 20-25). [8697495] (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2019-March). IEEE Computer Society. https://doi.org/10.1109/ISQED.2019.8697495

A General Framework to Map Neural Networks onto Neuromorphic Processor. / Fang, Haowen; Shrestha, Amar; Zhao, Ziyi; Wang, Yanzhi; Qiu, Qinru.

Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. p. 20-25 8697495 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2019-March).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fang, H, Shrestha, A, Zhao, Z, Wang, Y & Qiu, Q 2019, A General Framework to Map Neural Networks onto Neuromorphic Processor. in Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019., 8697495, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2019-March, IEEE Computer Society, pp. 20-25, 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, United States, 3/6/19. https://doi.org/10.1109/ISQED.2019.8697495
Fang H, Shrestha A, Zhao Z, Wang Y, Qiu Q. A General Framework to Map Neural Networks onto Neuromorphic Processor. In Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society. 2019. p. 20-25. 8697495. (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2019.8697495
Fang, Haowen ; Shrestha, Amar ; Zhao, Ziyi ; Wang, Yanzhi ; Qiu, Qinru. / A General Framework to Map Neural Networks onto Neuromorphic Processor. Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. pp. 20-25 (Proceedings - International Symposium on Quality Electronic Design, ISQED).
@inproceedings{7f45661ea54f44ee9485bd716392c4b7,
title = "A General Framework to Map Neural Networks onto Neuromorphic Processor",
abstract = "Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67{\%}, and reduces 53{\%} of communication latency.",
keywords = "Neuromorphic hardware, spiking neural network",
author = "Haowen Fang and Amar Shrestha and Ziyi Zhao and Yanzhi Wang and Qinru Qiu",
year = "2019",
month = "4",
day = "23",
doi = "10.1109/ISQED.2019.8697495",
language = "English (US)",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
pages = "20--25",
booktitle = "Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019",
address = "United States",

}

TY - GEN

T1 - A General Framework to Map Neural Networks onto Neuromorphic Processor

AU - Fang, Haowen

AU - Shrestha, Amar

AU - Zhao, Ziyi

AU - Wang, Yanzhi

AU - Qiu, Qinru

PY - 2019/4/23

Y1 - 2019/4/23

N2 - Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67%, and reduces 53% of communication latency.

AB - Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67%, and reduces 53% of communication latency.

KW - Neuromorphic hardware

KW - spiking neural network

UR - http://www.scopus.com/inward/record.url?scp=85065191445&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85065191445&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2019.8697495

DO - 10.1109/ISQED.2019.8697495

M3 - Conference contribution

AN - SCOPUS:85065191445

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 20

EP - 25

BT - Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019

PB - IEEE Computer Society

ER -