In this paper, we introduce a systematic methodology based on the concept of delay distribution to optimize the systolic scheduling of data flow graphs, which represent one-dimensional (1-D) linear recurrence algorithms (LRA’s). After this, step-by-step examples are given to illustrate the procedure. Then we show that this procedure produces optimally scheduled data flow graphs (DFG’s) for VLSI systolic implementation. Our goal, in this paper, is to transform the DFG of a linear recurrence algorithm into an optimal form for VLSI systolic implementation. Considerable improvements have been achieved over previous works. Comparisons are made between our and previous designs on the examples of infinite impulse response (IIR) filters and finite impulse response (FIR) filters. Finally, a generalization of the procedure to/V-dimensional linear recurrence algorithms is given, using the 1-D case as its basis.
|Original language||English (US)|
|Number of pages||13|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Jun 1991|
ASJC Scopus subject areas
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering