A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

Keyphrases

• Expected Energy 40%
• Cell Stability 20%
• Sentaurus 20%
• Tool Suite 20%
• TCAD Tool 20%
• Energy-efficient SRAM 20%
• Dual Gate 20%
• Back-gate Control 20%
• Leakage Energy 20%
• Back Gate 20%
• Energy-efficient Memory 20%
• Process Corners 20%
• Synopsys TCAD 20%
• Gate Control 20%
• Parametric Yield 20%
• Memory Cell 20%
• Transistor Size 20%
• External Signal 20%
• Front Gate 20%

Material Science

• Electronic Circuit 100%
• Analytical Method 100%
• Transistor 100%

Engineering

• Reduce Leakage 20%
• Clock Cycle 20%
• Operating Cell 20%
• External Signal 20%