A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In particular, 7nm FinFET devices are designed and simulated by using Synopsys TCAD tool suite, Sentaurus. Next, 6T and 8T SRAM cells, which are composed of these devices, are designed and optimized. To enhance the cell stability and reduce leakage energy consumption, the dual (i.e., front and back) gate control feature of FinFETs is exploited. This is, however, done without requiring any external signal to drive the back gates of the FinFET devices. Subsequently, the effect of process variations on the aforesaid SRAMs is investigated and steps are presented to protect the cells against these variations. More precisely, the SRAM cells are first designed to minimize the expected energy consumption (per clock cycle) subject to the non-destructive read and successful write requirements under worst-case process corner conditions. These SRAM cells, which are overly pessimistic, are then refined by selectively adjusting some transistor sizes, which in turn reduces the expected energy consumption while ensuring that the parametric yield of the cells remains above some prespecified threshold. To do this efficiently, an analytical method for estimating the yield of SRAM cells under process variations is also presented and integrated in the refinement procedure. A dual-gate controlled 6T SRAM cell operating at 324mV (in the near-threshold supply regime) is finally presented as a high-yield and energy-efficient memory cell in the 7nm FinFET technology.

Original languageEnglish (US)
Title of host publication20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages75-80
Number of pages6
ISBN (Electronic)9781479977925
DOIs
StatePublished - Mar 11 2015
Event2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
Duration: Jan 19 2015Jan 22 2015

Publication series

Name20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
CountryJapan
CityChiba
Period1/19/151/22/15

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modeling and Simulation

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    Shafaei, A., Chen, S., Wang, Y., & Pedram, M. (2015). A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 75-80). [7058984] (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058984