A cross-layer framework for designing and optimizing deeply-scaled finfet-based cache memories

Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and near-threshold modes of operation. Initially, at the device-level, seven FinFET devices on a 7-nm process technology are designed in which only one geometry-related parameter (e.g., fin width, gate length, gate underlap) is changed per device. Next, at the circuit-level, standard 6T and 8T SRAM cells made of these 7-nm FinFET devices are characterized and compared in terms of static noise margin, access latency, leakage power consumption, etc. Finally, cache memories with all different combinations of devices and SRAM cells are evaluated at the architecture-level using a modified version of the CACTI tool with FinFET support and other considerations for deeply-scaled technologies. Using this design framework, it is observed that L1 cache memory made of longer channel FinFET devices operating at the near-threshold regime achieves the minimum energy operation point.

Original languageEnglish (US)
Pages (from-to)165-182
Number of pages18
JournalJournal of Low Power Electronics and Applications
Volume5
Issue number3
DOIs
StatePublished - 2015
Externally publishedYes

Keywords

  • Cache memories
  • Deeply-scaled technologies
  • FinFET devices
  • Memory design

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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