A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices

Alireza Shafaei; Shuang Chen; Yanzhi Wang; Massoud Pedram

doi:10.1109/S3S.2014.7028219

A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices

Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram

Research output: Chapter in Book/Entry/Poem › Conference contribution

Original language	English (US)
Title of host publication	2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479974382
DOIs	https://doi.org/10.1109/S3S.2014.7028219
State	Published - Jan 30 2014
Externally published	Yes
Event	2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 - Millbrae, United States Duration: Oct 6 2014 → Oct 9 2014

Publication series

Name	2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014

Other

Other	2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
Country/Territory	United States
City	Millbrae
Period	10/6/14 → 10/9/14

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/S3S.2014.7028219

Cite this

Shafaei, A., Chen, S., Wang, Y., & Pedram, M. (2014). A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices. In 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 Article 7028219 (2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2014.7028219

A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices. / Shafaei, Alireza; Chen, Shuang; Wang, Yanzhi et al.
2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 7028219 (2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014).

Research output: Chapter in Book/Entry/Poem › Conference contribution

Shafaei, A, Chen, S, Wang, Y & Pedram, M 2014, A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices. in 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014., 7028219, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014, Institute of Electrical and Electronics Engineers Inc., 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014, Millbrae, United States, 10/6/14. https://doi.org/10.1109/S3S.2014.7028219

Shafaei A, Chen S, Wang Y, Pedram M. A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices. In 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 7028219. (2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014). doi: 10.1109/S3S.2014.7028219

Shafaei, Alireza ; Chen, Shuang ; Wang, Yanzhi et al. / A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices. 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014).

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A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices

Publication series

Other

ASJC Scopus subject areas

Access to Document

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