Find Research Outputs

Search concepts
Selected Filters

Publication Year

  • 2019
  • 2017
  • 2015

Author

  • Chien Yi Roger Chen
2015

Lookup table based discrete gate sizing for delay minimization with modified elmore delay model

Xie, J. & Chen, C. Y. R., May 20 2015, GLSVLSI 2015 - 25th 2015 Great Lakes Symposium on VLSI. Association for Computing Machinery, Vol. 20-22-May-2015. p. 361-366 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations