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2016
6 Citations (Scopus)

Leakage power reduction using the body bias and pin reordering technique

Chun, J. W. & Chen, C. Y. R., Jan 18 2016, In : IEICE Electronics Express. 13, 3

Research output: Contribution to journalLetter

leakage
Networks (circuits)
CMOS
Electric power utilization
optimization
3 Citations (Scopus)

Transistor and pin reordering for leakage reduction in CMOS circuits

Chun, J. W. & Chen, C. Y. R., Jul 1 2016, In : Microelectronics Journal. 53, p. 25-34 10 p.

Research output: Contribution to journalArticle

Leakage currents
CMOS
Transistors
leakage
transistors
2015
2 Citations (Scopus)

Lookup table based discrete gate sizing for delay minimization with modified elmore delay model

Xie, J. & Chen, C. Y. R., May 20 2015, GLSVLSI 2015 - 25th 2015 Great Lakes Symposium on VLSI. Association for Computing Machinery, Vol. 20-22-May-2015. p. 361-366 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Networks (circuits)