Abstract
Gate-all-around (GAA) FETs is proposed as a choice for deeply scaled MOSFETs beyond the 10 nm technology node. In this paper, we present a device and circuit (8T SRAM) co-simulation work based on Junctionless-GAA (JL-GAA) FETs. The same doping concentration level in channel and source/drain can mitigate fabrication complexity and process variability. The 8T SRAM monte carlo simulation results considering process variations shows JL-GAA FETs can reliably operate at low supply voltage.
Original language | English (US) |
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Title of host publication | 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781509002597 |
DOIs | |
State | Published - Nov 20 2015 |
Externally published | Yes |
Event | IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States Duration: Oct 5 2015 → Oct 8 2015 |
Other
Other | IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 |
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Country | United States |
City | Rohnert Park |
Period | 10/5/15 → 10/8/15 |
Keywords
- cross layer simulation
- gate-all-around (GAA)
- junctionless
- monte carlo simulation
- process variation
- SRAM
ASJC Scopus subject areas
- Electrical and Electronic Engineering