10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation

Luhao Wang; Alireza Shafaei; Shuang Chen; Yanzhi Wang; Shahin Nazarian; Massoud Pedram

doi:10.1109/S3S.2015.7333552

10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation

Luhao Wang, Alireza Shafaei, Shuang Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram

Department of Electrical Engineering & Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Gate-all-around (GAA) FETs is proposed as a choice for deeply scaled MOSFETs beyond the 10 nm technology node. In this paper, we present a device and circuit (8T SRAM) co-simulation work based on Junctionless-GAA (JL-GAA) FETs. The same doping concentration level in channel and source/drain can mitigate fabrication complexity and process variability. The 8T SRAM monte carlo simulation results considering process variations shows JL-GAA FETs can reliably operate at low supply voltage.

Original language	English (US)
Title of host publication	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509002597
DOIs	https://doi.org/10.1109/S3S.2015.7333552
State	Published - Nov 20 2015
Event	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States Duration: Oct 5 2015 → Oct 8 2015

Publication series

Name	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Other

Other	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Country/Territory	United States
City	Rohnert Park
Period	10/5/15 → 10/8/15

Keywords

SRAM
cross layer simulation
gate-all-around (GAA)
junctionless
monte carlo simulation
process variation

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/S3S.2015.7333552

Cite this

Wang, L., Shafaei, A., Chen, S., Wang, Y., Nazarian, S., & Pedram, M. (2015). 10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 [7333552] (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2015.7333552

10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation. / Wang, Luhao; Shafaei, Alireza; Chen, Shuang et al.

2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7333552 (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, L, Shafaei, A, Chen, S, Wang, Y, Nazarian, S & Pedram, M 2015, 10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation. in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015., 7333552, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Institute of Electrical and Electronics Engineers Inc., IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Rohnert Park, United States, 10/5/15. https://doi.org/10.1109/S3S.2015.7333552

Wang L, Shafaei A, Chen S, Wang Y, Nazarian S, Pedram M. 10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7333552. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). doi: 10.1109/S3S.2015.7333552

Wang, Luhao ; Shafaei, Alireza ; Chen, Shuang et al. / 10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

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10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation

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