@inproceedings{62ec04b8e4464816980b0f6bb46522a6,
title = "10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation",
abstract = "Gate-all-around (GAA) FETs is proposed as a choice for deeply scaled MOSFETs beyond the 10 nm technology node. In this paper, we present a device and circuit (8T SRAM) co-simulation work based on Junctionless-GAA (JL-GAA) FETs. The same doping concentration level in channel and source/drain can mitigate fabrication complexity and process variability. The 8T SRAM monte carlo simulation results considering process variations shows JL-GAA FETs can reliably operate at low supply voltage.",
keywords = "SRAM, cross layer simulation, gate-all-around (GAA), junctionless, monte carlo simulation, process variation",
author = "Luhao Wang and Alireza Shafaei and Shuang Chen and Yanzhi Wang and Shahin Nazarian and Massoud Pedram",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 ; Conference date: 05-10-2015 Through 08-10-2015",
year = "2015",
month = nov,
day = "20",
doi = "10.1109/S3S.2015.7333552",
language = "English (US)",
series = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",
}