Computer Science
Multiport Memory
100%
Experimental Result
75%
Performance Evaluation
75%
multistage interconnection network
75%
Interconnection Networks
58%
Multimedia Information
52%
Synchronous Circuit
50%
Multimedia Information System
50%
Concurrent Error Detection
50%
Time Complexity
50%
Efficient Algorithm
50%
Routing Algorithm
50%
And Gate
50%
Routing Channel
50%
Channel Density
50%
Multimedia Object
50%
Optimization Algorithm
50%
Parallel Access
50%
Allocation Strategy
50%
Parallel Circuit
50%
Multimedia
50%
Logic Array
37%
queueing model
37%
Read Only Memory
35%
Pipelining
31%
Functional Unit
27%
Traffic Pattern
25%
Future Direction
25%
Responder
25%
Data Interoperability
25%
fault-tolerance
25%
Data Management
25%
Distributed Multimedia Database System
25%
And-States
25%
Application Specific Integrated Circuit
25%
Matching Algorithm
25%
Network Topology
25%
Assignment Problem
25%
Multiple Instance
25%
Physical Implementation
25%
Interconnect Delay
25%
Top down Design
25%
time-delay
25%
Global Routing
25%
Information Processing
25%
Storage Technology
25%
Smoothing Algorithm
25%
Local Area Network
25%
Collision Detection
25%
Tolerance Technique
25%
Engineering
Experimental Result
87%
Multistage
81%
Cell Design
75%
Hierarchical Pin
50%
Performance Analysis
50%
Routing Algorithm
50%
Efficient Allocation
50%
Speed Memory
50%
Bipartite Graph
50%
Switching Function
50%
Nanometre
37%
Switching Circuit
31%
Responder
25%
Functional Abstraction
25%
Design Information
25%
Redundant Information
25%
Physical Size
25%
Data Representation
25%
Automation System
25%
Concurrent Error Detection
25%
Microprocessor Chips
25%
Bit Line
25%
Propagation Delay
25%
Delay Circuits
25%
Design Cycle
25%
Multiport Memory
25%
Polysilicon
25%
Data Path
25%
Dynamic Power Dissipation
25%
Horizontal Row
25%
Tasks
25%
Logic Gate
25%
Cross Point
25%
Relational
25%
Negative Effect
25%
Clock Edge
25%
Sequencer
25%
Linear Time
25%
Constraint Length
25%
Layout Optimization
25%
Distributed Multimedia Application
25%
Application Layer
25%
Matching Algorithm
25%
Tunnel Construction
25%
Rise Time
25%
Fall Time
25%
Early Phase
25%
Loading Effect
25%
Placers
25%
High Level Synthesis
25%
Keyphrases
Multistage Interconnection Networks
100%
Performance Evaluation
62%
Synchronous Circuit
50%
Path Synthesis
50%
Multi-port Memory
50%
Performance Analysis
50%
Channel Density
50%
Channel Routing
50%
Permutation Algorithms
50%
Circuit Switching
50%
Grouped Variables
33%
Router
33%
Switching Element
27%
Vacation Queue
25%
Data Interoperability
25%
Banyan Network
25%
Markov Modulated Bernoulli Process
25%
Incident Command
25%
Circuit Description
25%
Design Automation System
25%
Switchover Times
25%
Message Routing
25%
Concurrent Error Detection
25%
Read Only Memory
25%
Reordering Techniques
25%
Edge Algorithm
25%
CMOS Circuit Design
25%
Leakage Power Reduction
25%
Bitline
25%
Power Reduction Techniques
25%
Wire Width
25%
CMOS VLSI
25%
Layout Generation
25%
Systolic Architecture
25%
Polysilicon
25%
Post-processor
25%
Smoothing Algorithm
25%
Recurrence Algorithm
25%
MPEG-2
25%
Delay Distribution
25%
Linear Recurrence
25%
Interconnection System
25%
Carrier Sense multiple Access
25%
Local Area Networks
25%
Collision Detection
25%
Gate Location
25%
Terminal Position
25%
Optimal Routing
25%
Permutable
25%
Standard Cell Design
25%
