• 585 Citations
  • 13 h-Index
1985 …2016
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Fingerprint Dive into the research topics where Chien Yi Roger Chen is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

Networks (circuits) Engineering & Materials Science
Transistors Engineering & Materials Science
Data storage equipment Engineering & Materials Science
Switching networks Engineering & Materials Science
Routers Engineering & Materials Science
Routing algorithms Engineering & Materials Science
Error detection Engineering & Materials Science
Placers Engineering & Materials Science

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Research Output 1985 2016

6 Citations (Scopus)

Leakage power reduction using the body bias and pin reordering technique

Chun, J. W. & Chen, C. Y. R., Jan 18 2016, In : IEICE Electronics Express. 13, 3

Research output: Contribution to journalLetter

leakage
Networks (circuits)
CMOS
Electric power utilization
optimization
3 Citations (Scopus)

Transistor and pin reordering for leakage reduction in CMOS circuits

Chun, J. W. & Chen, C. Y. R., Jul 1 2016, In : Microelectronics Journal. 53, p. 25-34 10 p.

Research output: Contribution to journalArticle

Leakage currents
CMOS
Transistors
leakage
transistors
2 Citations (Scopus)

Lookup table based discrete gate sizing for delay minimization with modified elmore delay model

Xie, J. & Chen, C. Y. R., May 20 2015, GLSVLSI 2015 - 25th 2015 Great Lakes Symposium on VLSI. Association for Computing Machinery, Vol. 20-22-May-2015. p. 361-366 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Table lookup
Networks (circuits)
1 Citation (Scopus)

A tool to generate models based on behavioral IBIS models

Deepaksubramanyan, B. S., Chen, C. Y. R. & Nunez, A., 2012, Midwest Symposium on Circuits and Systems. p. 234-237 4 p. 6292000

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Buffers
Specifications
Networks (circuits)
Poles
Weibull distribution
19 Citations (Scopus)

A novel leakage power reduction technique for CMOS circuit design

Chun, J. W. & Chen, C. Y. R., 2010, 2010 International SoC Design Conference, ISOCC 2010. p. 119-122 4 p. 5682957

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Transistors
Electric power utilization
SPICE
Oxides